DVDD
DGND
AGND1
AVDD1
AGND2
AVDD2
SCLK
DI
DO
CS
DAC
SD
Tx_FLAG
Rx_FLAG
INT
REF1
REF2
ZC_OUT2
ZC_OUT1
ZC_IN1
ZC_IN2
PA_ISET
PA_VS
PA_GND
TSENSE
PA_OUT
E_Rx_IN
E_Rx_OUT
E_Tx_CLK
E_Tx_IN
E_Tx_OUT
Rx_PGA1_IN
Rx_PGA1_OUT
Rx_F_IN
Rx_C1
Rx_C2
Rx_F_OUT
Tx_PGA_IN
TX_PGA_OUT
Tx_F_IN1
Tx_F_IN2
Tx_F_OUT
PA_IN
Rx_PGA2_OUT
Rx_PGA2_IN
Bias ZC2
ZC1
Power
Amplifier
Digital Interface
(SPI)
Control
Register
Digital-to-Analog
Converter TxPGA
RxPGA_1
RxPGA_2
Tx Filter
Rx Filter
Two-Wire Rx/Tx
AFE031
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
Powerline Communications
Analog Front-End
Check for Samples: AFE031
1FEATURES DESCRIPTION
The AFE031 is a low-cost, integrated, powerline
234• Integrated Powerline Driver with Thermal and communications (PLC) analog front-end (AFE) device
Overcurrent Protection that is capable of capacitive- or transformer-coupled
• Conforms to EN50065-1 connections to the powerline while under the control
• PRIME Certified of a DSP or microcontroller. It is ideal for driving low-
impedance lines that require up to 1.5 A into reactive
• Large Output Swing: 12 VPP at 1.5 A loads. The integrated receiver is able to detect
(15-V Supply) signals down to 20 μVRMS and is capable of a wide
• Low Power Consumption: range of gain options to adapt to varying input signal
15 mW (Receive Mode) conditions. This monolithic integrated circuit provides
high reliability in demanding powerline
• Programmable Tx and Rx Filters communications applications.
• Supports EN50065 CENELEC Bands A, B, C, D The AFE031 transmit power amplifier operates from a
• Supports FSK, S-FSK, and OFDM single supply in the range of 7 V to 24 V. At
• Supports PRIME, G3, IEC 61334 maximum output current, a wide output swing
• Receive Sensitivity: 20 μVRMS, Typical provides a 12-VPP (IOUT = 1.5 A) capability with a
nominal 15-V supply. The analog and digital signal
• Programmable Tx and Rx Gain Control processing circuitry operates from a single 3.3-V
• Four-Wire Serial Peripheral Interface power supply.
• Two Integrated Zero Crossing Detectors The AFE031 is internally protected against
• Two-Wire Transceiver Buffer overtemperature and short-circuit conditions. It also
• 48-Pin QFN PowerPAD™ Package provides an adjustable current limit. An interrupt
output is provided that indicates both current limit and
• Extended Junction Temperature Range: thermal limit. There is also a shutdown pin that can
–40°C to +125°C be used to quickly put the device into its lowest
power state. Through the four-wire serial peripheral
APPLICATIONS interface, or SPI™, each functional block can be
• eMetering enabled or disabled to optimize power dissipation.
• Lighting The AFE031 is housed in a thermally-enhanced,
• Solar surface-mount PowerPAD package (QFN-48).
Operation is specified over the extended industrial
• Pilot Wire junction temperature range of –40°C to +125°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD, C2000 are trademarks of Texas Instruments.
3SPI is a trademark of Motorola, Inc.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
AFE031AIRGZT QFN-48 PowerPAD RGZ AFE031A
AFE031AIRGZR QFN-48 PowerPAD RGZ AFE031A
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). VALUE UNIT
Supply voltage, PA_VS+26 V
Voltage(2) PA_GND – 0.4 to PA_VS+ 0.4 V
Signal input terminal,
pins 18,19 Current(2) ±10 mA
Supply voltage, AVDD +5.5 V
Signal input terminal, Voltage(2) AGND – 0.4 to AVDD + 0.4 V
pins 13, 15, 16, 21, 23, 24, 25, Current(2) ±10 mA
28, 32, 34, 35, 38, 39, 46
Signal input terminal, pin 27 Voltage limit ±10 V
Signal input terminal, pin 10 Current limit ±10 mA
Supply voltage, DVDD +5.5 V
Voltage(2) DGND – 0.4 to DVDD + 0.4 V
Signal input terminal,
pins 3, 4, 6, 7, 8 Current(2) ±10 mA
Signal output terminal,
pins 5, 9, 14, 17, 20, 22, 26, Current(2) Continuous
31, 33, 36, 37, 47, 48
Output short-circuit (PA), pins 42,43(2)(3)(4) Continuous
Operating temperature, TA(4) –40 to +150 °C
Storage temperature, TA–55 to +150 °C
Junction temperature, TJ+150 °C
Human body model (HBM) 3000 V
ESD ratings Machine model (MM) 200 V
Charged device model (CDM) 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.4 V beyond the supply rails should
be current limited to 10 mA or less. Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more
than 0.4 V beyond the supply rails should be current limited to 10 mA or less.
(3) Short-circuit to ground.
(4) The AFE031 automatically goes into shutdown at junction temperatures that exceed +150°C.
2Copyright © 2010–2012, Texas Instruments Incorporated
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SBOS531D –AUGUST 2010–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS: Transmitter (Tx)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
Tx_DAC
Output range GND + 0.1 AVDD – 0.1 V
Resolution 1,024 steps, 10-bit DAC 3.2 mV
Total harmonic distortion at THD
62.5 kHz(1)
Second harmonic distortion –73 dB
Third harmonic distortion –56 dB
Fourth harmonic distortion –94 dB
Data rate 1.5 MSPS
Tx_PGA
Input
Input voltage range GND – 0.1 AVDD + 0.1 V
G = 1 V/V 58 kΩ
G = 0.707 V/V 68 kΩ
Input resistance RIG = 0.5 V/V 77 kΩ
G = 0.25 V/V 92 kΩ
Frequency Response
DAC mode enabled
G = 1 V/V 8 MHz
Bandwidth BW G = 0.707 V/V 9 MHz
G = 0.5 V/V 10 MHz
G = 0.25 V/V 12 MHz
Output
Voltage output swing from VORLOAD = 10 kΩ, connected to AVDD/2 10 100 mV
AGND or AVDD Sourcing 25 mA
Maximum continuous IO
current, dc Sinking 25 mA
Output resistance ROf = 100 kHz 1 Ω
Gain
Gain error For all gains –1 ±0.1 +1 %
Gain error drift TJ= –40°C to +125°C 6 ppm/°C
(1) Total harmonic distortion measured at output of Tx_PGA configured in a gain of 1 V/V with an amplitude of 3 VPP, at a 1-MHz sample
rate.
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ELECTRICAL CHARACTERISTICS: Transmitter (Tx) (continued)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
Tx_FILTER
Input
Input voltage range GND – 0.1 AVDD + 0.1 V
Input resistance RI43 kΩ
(Tx_F_IN1 and Tx_F_IN2)
Frequency Response
CENELEC A Mode
Passband frequency –3 dB 95 kHz
Stop band attenuation –50 –60 dB
Stop band frequency 910 kHz
Filter gain 0 dB
CENELEC B/C/D Modes
Passband frequency –3 dB 145 kHz
Stop band attenuation –50 –60 dB
Stop band frequency 870 kHz
Filter gain 0 dB
Output
Voltage output swing from VORLOAD = 10 kΩ, connected to AVDD/2 10 100 mV
AGND or AVDD Sourcing 25 mA
Maximum continuous IO
current, dc Sinking 25 mA
Output resistance ROf = 100 kHz 1 Ω
Transmitter Noise
Integrated noise at PA output(2)
CENELEC Band A Noise-reducing capacitor = 1 nF from 435 μVRMS
(40 kHz to 90 kHz) pin 19 to ground
CENELEC Bands B/C/D Noise-reducing capacitor = 1 nF from 460 μVRMS
(95 kHz to 140 kHz) pin 19 to ground
(2) Includes DAC, Tx_PGA, Tx_Filter, PA, and REF1 bias generator.
4Copyright © 2010–2012, Texas Instruments Incorporated
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SBOS531D –AUGUST 2010–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS: Power Amplifier (PA)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
Input
PA_VS+
Input voltage range GND – 0.1 V
0.1
Input resistance RI20 kΩ
Frequency Response
Bandwidth BW ILOAD = 0 670 kHz
Slew rate SR 10-V step 19 V/μs
Full-power bandwidth VOUT = 10 VPP 300 kHz
AC PSRR f = 50 kHz 14 dB
Output
IO= 300 mA, sourcing 0.3 1 V
Voltage output swing from VO
PA_VSIO= 1.5 A, sourcing 1.7 2 V
IO= 300 mA, sinking 0.3 1 V
Voltage output swing from VO
PA_Gnd IO= 1.5 A, sinking 1.3 2 V
Maximum continuous current, dc IO7.5 kΩconnected to PA_ISET 1.5 A
Maximum peak current, ac TJ= –40°C to +125°C; f = 50 kHz 1.7 A
Output resistance ROIO= 1.5 A 0.1 Ω
PA disabled
Output impedance f = 100 kHz, REF1 enabled 145 ll 120 kΩll pF
Output current limit range ±0.4 to ±1.5 A
ILIM = 20 kΩ• [1.2 V/(RSET + 5 kΩ)] A
Current limit equation Solved for RSET (Current Limit) RSET = [(20 kΩ• 1.2 V/ILIM) – 5 kΩ]Ω
Gain RLOAD = 1 kΩ
Nominal gain G 6.5 V/V
Gain error –1 0.1 +1 %
Gain error drift TJ= –40°C to +125°C ±1 ppm/°C
TSENSE Diode
Diode ideality factor η1.033
Thermal Shutdown
Junction temperature at shutdown +160 °C
Hysteresis 15 °C
Return to normal operation +145 °C
Copyright © 2010–2012, Texas Instruments Incorporated 5
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ELECTRICAL CHARACTERISTICS: Receiver (Rx)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
Rx PGA1
Input
Input voltage range 10 VPP
G = 2 V/V 10 kΩ
G = 1 V/V 15 kΩ
Input resistance RIG = 0.5 V/V 20 kΩ
G = 0.25 V/V 24 kΩ
Frequency Response
G = 2 V/V 6 MHz
G = 1 V/V 10 MHz
Bandwidth BW G = 0.5 V/V 13 MHz
G = 0.25 V/V 15 MHz
Output
Voltage output swing from VORLOAD = 6 kΩ, connected to AVDD/2 10 100 mV
AGND or AVDD Sourcing 25 mA
Maximum continuous current, dc IOSinking 25 mA
Output resistance ROG = 1, f = 100 kHz 1 Ω
Gain
G = 0.25 V/V –1 ±0.1 +1 %
G = 0.5 V/V –1 ±0.1 +1 %
Gain error G = 1 V/V –1 ±0.1 +1 %
G = 2 V/V –2 ±0.2 +2 %
Gain error drift TJ= –40°C to +125°C 1 ppm/°C
Rx Filter
Input
Input voltage range GND – 0.1 AVDD + 0.1 V
Input resistance RIN 6 kΩ
Frequency Response
CENELEC A Mode Rx_C1 = 680 pF, Rx_C2 = 680 pF
Passband frequency –3 dB 90 kHz
Stop band attentuation –25 –33 dB
Stop band frequency 270 kHz
Filter gain 0 dB
CENELEC B/C/D Modes Rx_C1 = 270 pF, Rx_C2 = 560 pF
Passband frequency –3 dB 145 kHz
Stop band attentuation –23 –27 dB
Stop band frequency 350 kHz
Filter gain 0 dB
Output
Voltage output swing from VORLOAD = 10 kΩ, connected to AVDD/2 10 100 mV
AGND or AVDD Sourcing 25 mA
Maximum continuous current, dc IOSinking 25 mA
Output resistance ROf = 100 kHz 5 Ω
6Copyright © 2010–2012, Texas Instruments Incorporated
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SBOS531D –AUGUST 2010–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS: Receiver (Rx) (continued)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
Rx PGA2
Input
Input voltage range GND – 0.1 AVDD + 0.1 V
G = 64 V/V 1.7 kΩ
G = 16 V/V 6.3 kΩ
Input impedance RIG = 4 V/V 21 kΩ
G = 1 V/V 53 kΩ
Frequency Response
G = 64 V/V 300 kHz
G = 16 V/V 800 kHz
Bandwidth BW G = 4 V/V 1.4 MHz
G = 1 V/V 4 MHz
Output
Voltage output swing from VORLOAD = 10 kΩ, connected to AVDD/2 10 100 mV
AGND or AVDD Sourcing 25 mA
Maximum continuous current, dc IOSinking 25 mA
Output impedance ROG = 1, f = 100 kHz 1 Ω
Gain
G = 1 V/V –2 ±1 2 %
G = 4 V/V –2 ±1 2 %
Gain error G = 16 V/V –2 ±1 2 %
G = 64 V/V –4 ±1 4 %
Gain error drift TJ= –40°C to +125°C 6 ppm/°C
Rx Sensitivity
Integrated noise, RTI(1)
CENELEC Band A Noise-reducing capacitor = 1 μF from 14 μVRMS
(40 kHz to 90 kHz) pin 28 to ground
CENELEC Bands B/C/D Noise-reducing capacitor = 1 μF from 11 μVRMS
(95 kHz to 140 kHz) pin 28 to ground
(1) Includes Rx PGA1, Rx_Filter, Rx PGA2, and REF2 bias generator.
Copyright © 2010–2012, Texas Instruments Incorporated 7
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ELECTRICAL CHARACTERISTICS: Digital
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
Digital Inputs (SCLK, DIN, CS, DAC, SD)
Leakage input current 0 ≤VIN ≤DVDD –1 0.01 1 μA
Input logic levels
High-level input voltage VIH 0.7 • DVDD V
Low-level input voltage VIL 0.3 • DVDD V
SD pin high SD > 0.7 • DVDD AFE031 in shutdown
SD pin low SD < 0.3 • DVDD AFE031 in normal operation
DAC pin high DAC > 0.7 • DVDD SPI access to DAC Register
SPI access to Command and Data
DAC pin low DAC < 0.3 • DVDD Registers
Digital Outputs (DO, ZC_OUT)
VO
High-level output voltage IOH = 3 mA DVDD – 0.4 DVDD V
H
Low-level output voltage VOL IOL = –3 mA GND GND + 0.4 V
Digital Outputs (INT, Tx_Flag, Rx_Flag)
High-level output current IOH VOH = 3.3 V 1 μA
Low-level output voltage VOL IOL = 4 mA 0.4 V
Low-level output current IOL VOL = 400 mV 4 mA
INT pin high (open drain) INT sink current < 1 μA Normal operation
INT pin low (open drain)(1) INT < 0.4 V Indicates an interrupt has occurred
Tx_Flag high (open drain) Tx_Flag sink current < 1 μA Indicates Tx block is ready
Tx_Flag low (open drain) Tx_Flag < 0.4 V Indicates Tx block is not ready
Rx_Flag high (open drain) Rx_Flag sink current < 1 μA Indicates Rx block is ready
Rx_Flag low (open drain) Rx_Flag < 0.4 V Indicates Rx block is not ready
DIGITAL TIMING
Gain Timing
Gain select time 0.2 μs
Shutdown Mode Timing
Enable time 4.0 μs
Disable time 2.0 μs
POR Timing
Power-On Reset power-up time DVDD ≥2 V 50 μs
(1) When an interrupt is detected (INT pin low), the contents of the I_Flag and T_Flag Registers can be read to determine the reason for the
interrupt.
8Copyright © 2010–2012, Texas Instruments Incorporated
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SBOS531D –AUGUST 2010–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS: Two-Wire Interface
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
TWO-WIRE TRANSMITTER
Frequency range(1) 50 kHz
Leakage input current 0≤VIN ≤DVDD –1 0.01 1 μA
(E_Tx_In, E_Tx_Clk)
Input logic levels (E_Tx_In, E_Tx_Clk)
High-level input voltage VIH 0.7 • DVDD V
Low-level input voltage VIL 0.3 • DVDD V
Output logic levels (E_Tx_Out) VO
High-level output voltage IOH = 3 mA AVDD – 0.4 AVDD V
H
Low-level output voltage VOL IOL = –3 mA GND GND + 0.4 V
TWO-WIRE RECEIVER
Gain –4.5 dB
Frequency range 300 kHz
Max sink current 25 mA
Max source current 25 mA
Input terminal offset Referenced to VAVDD/2 –100 10 100 mV
Input impedance 78 kΩ
ZERO CROSSING DETECTOR
Input voltage range AVDD – 0.4 AVDD + 0.4 V
Input current range –10 +10 mA
Input capacitance 3 pF
Rising threshold 0.45 0.9 1.35 V
Falling threshold 0.25 0.5 0.75 V
Hysteresis 0.20 0.4 0.60 V
Jitter 50 Hz, 240 VRMS 10 ns
(1) The two-wire transmitter circuit is tested at Tx_CLK = 10 MHz.
ELECTRICAL CHARACTERISTICS: Internal Bias Generator
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
REF1 (Pin 19)
Bias voltage PA_VS/2 V
Input resistance RI4 kΩ
Noise-reducing capacitor = 1 nF from
Turn-on time 20 ms
pin 19 to ground
Noise-reducing capacitor = 1 nF from
Turn-off time 20 ms
pin 19 to ground
REF2 (Pin 28)
Bias voltage VAVDD/2 V
Input resistance RI4 kΩ
Noise-reducing capacitor = 1 μF from
Turn-on time 20 ms
pin 28 to ground
Noise-reducing capacitor = 1 μF from
Turn-off time 20 ms
pin 28 to ground
Copyright © 2010–2012, Texas Instruments Incorporated 9
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ELECTRICAL CHARACTERISTICS: Power Supply
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
AFE031
PARAMETER CONDITIONS MIN TYP MAX UNIT
Operating Supply Range
Power amplifier supply voltage PA_VS+7 +24 V
Digital supply voltage DVDD +3.0 +3.6 V
Analog supply voltage AVDD +3.0 +3.6 V
Quiescent Current SD pin low
IO= 0, PA = On(1) 49 61 mA
Power amplifier current IQPA_VS IO= 0, PA = Off(2) 10 μA
Tx configuration(3) 1.2 mA
Digital supply current IQDVDD Rx configuration(4) 5μA
All blocks disabled(5) 5μA
Tx configuration(3) 2.8 3.7 mA
Analog supply current IQAVDD Rx configuration(4) 3.6 5.3 mA
All blocks disabled(5) 30 μA
Shutdown (SD)
Power amplifier supply voltage PA_VSSD pin high 75 150 μA
Digital supply voltage DVDD SD pin high 5 10 μA
Analog supply voltage AVDD SD pin high 15 40 μA
Temperature
Specified range –40 +125 °C
(1) Enable1 Register = 00100011, Enable2 Register = 00001110.
(2) Enable1 Register = 00000100, Enable2 Register = 00000110.
(3) In the Tx configuration, the following blocks are enabled: DAC, Tx, PA, REF1, and REF2. All other blocks are disabled. Enable1
Register = 00100011, Enable2 Register = 00001110.
(4) In the Rx configuration, the following blocks are enabled: Rx, REF1, and REF2. All other blocks are disabled. Enable1 Register =
00000100, Enable2 Register = 00000110.
(5) Enable1 Register = 00000000, Enable2 Register = 00000000.
THERMAL INFORMATION AFE031
THERMAL METRIC(1) RGZ (QFN) UNITS
48 PINS
θJA Junction-to-ambient thermal resistance 27.8
θJCtop Junction-to-case (top) thermal resistance 12.1
θJB Junction-to-board thermal resistance 7.5 °C/W
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 7.4
θJCbot Junction-to-case (bottom) thermal resistance 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
10 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
CS
SCLK
DIN
DOUT
tCSSC
tSU tHD
tLO tHI
tDO tSOZ
tCS1 tCS0
tSCCS
tCSH
1/fSCLK
Hi-Z Hi-Z
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
SPI TIMING REQUIREMENTS
PARAMETER CONDITION MIN TYP MAX UNIT
Input capacitance 1 pF
Input rise/fall time tRFI CS, DIN, SCLK 2 ns
Output rise/fall time tRFO DOUT 10 ns
CS high time tCSH CS 20 ns
SCLK edge to CS fall setup time tCS0 10 ns
CS fall to first SCLK edge setup time tCSSC 10 ns
SCLK frequency fSCLK 20 MHz
SCLK high time tHI 20 ns
SCLK low time tLO 20 ns
SCLK last edge to CS rise setup time tSCCS 10 ns
CS rise to SCLK edge setup time tCS1 10 ns
DIN setup time tSU 10 ns
DIN hold time tHD 5 ns
SCLK to DOUT valid propagation delay tDO 20 ns
CS rise to DOUT forced to Hi-Z tsoz 20 ns
TIMING DIAGRAMS
Figure 1. SPI Mode 0,0
Copyright © 2010–2012, Texas Instruments Incorporated 11
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CS
SDI
SDO
R0 R1 R2 R3
XX D0 D1 D2 D3
Any Command
R - Command of Read Register Read
D - Data from Register
XX - Don’t care; undefined.
N
N
CS
SDI
SDO
W0 W1 W2 W3
XX XX XX XX
W - Command of Write Register
XX - Don’t care; undefined.
N
CS
SCLK
DIN
DOUT
tCSSC
tSU tHD
tLO
tHI
tDO tSOZ
tCS1 tCS0
tSCCS
tCSH
1/fSCLK
Hi-Z Hi-Z
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
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Figure 2. SPI Mode 1,1
Figure 3. Write Operation in Stand-Alone Mode
Figure 4. Read Operation in Stand-Alone Mode
12 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
DGND
Tx_PGA_IN
DVDD
Tx_PGA_OUT
SCLK
Tx_F_IN1
DIN
Tx_F_IN2
DOUT
Tx_F_OUT
CS
PA_IN
DAC
REF1
SD
Rx_PGA2_OUT
INT
Rx_PGA2_IN
TSENSE
Rx_F_OUT
AVDD1
Rx_C2
AGND1
ZC_OUT2
E_Tx_CLK
E_Tx_IN
E_Tx_OUT
E_Rx_IN
E_Rx_OUT
AVDD2
AGND2
REF2
Rx_PGA1_IN
Rx_PGA1_OUT
Rx_F_IN
Rx_C1
Rx_FLAG
Tx_FLAG
PA_ISET
PA_VS1
PA_VS2
PA_OUT1
PA_OUT2
PA_GND1
PA_GND2
ZC_IN1
ZC_IN2
ZC_OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13 48
14 47
15 46
16 45
17 44
18 43
19 42
20 41
21 40
22 39
23 38
24 37
25
26
27
28
29
30
31
32
33
34
35
36
Thermal Pad
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
DEVICE INFORMATION
PIN ASSIGNMENTS
RGZ PACKAGE
QFN-48
(TOP VIEW)
NOTE: Exposed thermal pad is connected to ground.
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SBOS531D –AUGUST 2010–REVISED MAY 2012
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PIN DESCRIPTIONS
AFE031
PIN NO. NAME DESCRIPTION
1 DGND Digital ground
2 DVDD Digital supply
3 SCLK SPI serial clock
4 DIN SPI digital input
5 DOUT SPI digital output
6 CS SPI digital chip select
7 DAC DAC mode select
8 SD System shutdown
9 INT Interrupt on overcurrent or thermal limit
10 TSENSE Temp sensing diode (anode)
11 AVDD1 Analog lupply
12 AGND1 Analog ground
13 Tx_PGA_IN Transmit PGA lnput
14 Tx_PGA_OUT Transmit PGA lutput
15 Tx_F_IN1 Transmit filter input 1
16 Tx_F_IN2 Transmit filter input 2
17 Tx_F_OUT Transmit filter output
18 PA_IN Power Amplifier input
19 REF1 Power Amplifier noise reducing capacitor
20 Rx PGA2_OUT Receiver PGA(2) output
21 Rx PGA2_IN Receiver PGA(2) input
22 Rx_F_OUT Receiver filter output
23 Rx_C2 Receiver external frequency select
24 Rx_C1 Receiver external frequency select
25 Rx_F_IN Receiver filter input
26 Rx PGA1_OUT Receiver PGA(1) output
27 Rx PGA1_IN Receiver PGA(1) input
28 REF2 Receiver noise reducing capacitor
29 AGND2 Analog ground
30 AVDD2 Analog supply
31 E_Rx_OUT Two-wire receiver output
32 E_Rx_IN Two-wire receiver input
33 E_Tx_OUT Two-wire transmitter output
34 E_Tx_IN Two-wire transmitter input
35 E_Tx_CLK Two-wire transmitter clock input
36 ZC_OUT2 Zero crossing detector output
37 ZC_OUT1 Zero crossing detector output
38 ZC_IN2 Zero crossing detector input
39 ZC_IN1 Zero crossing detector input
40 PA_GND2 Power Amplifier ground
41 PA_GND1 Power Amplifier ground
42 PA_OUT2 Power Amplifier output
43 PA_OUT1 Power Amplifier output
44 PA_VS2 Power Amplifier supply
45 PA_VS1 Power Amplifier supply
46 PA_ISET Power Amplifier current limit set
47 Tx_FLAG Transmitter ready flag
48 Rx_FLAG Receiver ready flag
14 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
DVDD
DGND
AGND1
AVDD1
AGND2
AVDD2
SCLK
DI
DO
CS
DAC
SD
Tx_FLAG
Rx_FLAG
INT
REF1
REF2
ZC_OUT2
ZC_OUT1
ZC_IN1
ZC_IN2
PA_ISET
PA_VS
PA_GND
TSENSE
PA_OUT
E_Rx_IN
E_Rx_OUT
E_Tx_CLK
E_Tx_IN
E_Tx_OUT
Rx_PGA1_IN
Rx_PGA1_OUT
Rx_F_IN
Rx_C1
Rx_C2
Rx_F_OUT
Tx_PGA_IN
TX_PGA_OUT
Tx_F_IN1
Tx_F_IN2
Tx_F_OUT
PA_IN
Rx_PGA2_OUT
Rx_PGA2_IN
Bias ZC2
ZC1
Power
Amplifier
Digital Interface
(SPI)
Control
Register
Digital-to-Analog
Converter TxPGA
RxPGA_1
RxPGA_2
Tx Filter
Rx Filter
Two-Wire Rx/Tx
AFE031
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2010–2012, Texas Instruments Incorporated 15
Product Folder Link(s): AFE031
−40
−30
−20
−10
0
10
20
30
40
10k 100k 1M 10M 20M
Frequency (Hz)
Gain (dB)
Gain = 1 V/V
Gain = 0.707 V/V
Gain = 0.5 V/V
Gain = 0.25 V/V
G005
−40
−30
−20
−10
0
10
20
30
40
10k 100k 1M 10M 100M
Frequency (Hz)
Gain (dB)
Gain = 2 V/V
Gain = 1 V/V
Gain = 0.5 V/V
Gain = 0.25 V/V
G006
−40
−30
−20
−10
0
10
20
30
40
50
60
10k 100k 1M 10M
Frequency (Hz)
Gain (dB)
G003
0
5
10
15
20
25
1k 10k 100k 1M 10M
Frequency (Hz)
Maximum PA Output Voltage (VPP)
PA Supply = 24V
PA Supply = 15V
PA Supply = 12V
G004
−60
−50
−40
−30
−20
−10
0
10
20
10k 100k 1M
Frequency (Hz)
Gain (dB)
CENELEC A
CENELEC B,C,D
G001
−60
−50
−40
−30
−20
−10
0
10
20
10k 100k 1M
Frequency (Hz)
Gain (dB)
CENELEC A
CENELEC B,C,D
G002
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
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TYPICAL CHARACTERISTICS
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
Tx Filter GAIN vs FREQUENCY Rx Filter GAIN vs FREQUENCY
Figure 5. Figure 6.
PA GAIN vs FREQUENCY MAXIMUM PA OUTPUT VOLTAGE vs FREQUENCY
Figure 7. Figure 8.
Tx PGA GAIN vs FREQUENCY Rx PGA1 GAIN vs FREQUENCY
Figure 9. Figure 10.
16 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Gain Error (%)
G011
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Gain Error (%)
G012
50
75
100
125
150
175
200
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Cutoff Frequency (kHz)
CENELEC BCD, Tx and Rx
CENELEC A, Tx and Rx
G009
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Gain Error (%)
G010
−40
−30
−20
−10
0
10
20
30
40
50
60
10k 100k 1M 10M 100M
Frequency (Hz)
Gain (dB)
Gain = 64 V/V
Gain = 16 V/V
Gain = 4 V/V
Gain = 1 V/V
G007
−40
−30
−20
−10
0
10
20
10k 100k 1M
Frequency (Hz)
Gain (dB)
G008
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
Rx PGA2 GAIN vs FREQUENCY TWO-WIRE RECEIVER GAIN vs FREQUENCY
Figure 11. Figure 12.
FILTER CUTOFF vs TEMPERATURE Tx PGA GAIN ERROR vs TEMPERATURE
Figure 13. Figure 14.
PA GAIN ERROR vs TEMPERATURE Rx PGA1 GAIN ERROR vs TEMPERATURE
Figure 15. Figure 16.
Copyright © 2010–2012, Texas Instruments Incorporated 17
Product Folder Link(s): AFE031
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
010 µs/div (dB)
Voltage (V)
Tx Filter CENELEC A
Tx Filter CENELEC B
G017
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
01 µs/div (dB)
Voltage (V)
G018
0
20
40
60
80
100
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Supply Current (µA)
PA Current
AVDD Current
DVDD Current
All blocks disabled
G015
0
0.5
1
1.5
2
2.5
3
5 10 15 20 25 30 35 40 45 50
RSET (kΩ)
PA Current Limit (A)
+3σ
Typical
−3σ
G016
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Gain Error (%)
G013
0
10
20
30
40
50
60
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Supply Current (mA)
PA Current (PA Enabled)
AVDD Current (RX Mode)
AVDD Current (TX Mode)
G014
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
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TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
Rx PGA2 GAIN ERROR vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE
Figure 17. Figure 18.
SUPPLY CURRENT (SHUTDOWN) vs TEMPERATURE PA CURRENT LIMIT vs RSET
Figure 19. Figure 20.
Tx Filter PULSE RESPONSE PA PULSE RESPONSE
Figure 21. Figure 22.
18 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
010 µs/div (dB)
Voltage (V)
Rx Filter CENELEC A
Rx Filter CENELEC B
G019
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, PA_VS= 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩconnected to PA_ISET (pin 46), unless otherwise noted.
Rx PULSE RESPONSE
Figure 23.
Copyright © 2010–2012, Texas Instruments Incorporated 19
Product Folder Link(s): AFE031
Serial
Interface
Serial
Interface
DAC PGA
PGA PGA
LPF
LPF
PA
Line Coupling Interface
+ +
N1 N2
Bandpass Filter
C2000 MCU AFE031
Phase
Neutral
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
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APPLICATION INFORMATION
GENERAL DESCRIPTION
The AFE031 is an integrated powerline communication analog front-end (AFE) device built from a variety of
functional blocks that work in conjunction with a microcontroller. The AFE031 provides the interface between the
microcontroller and a line coupling circuit. The AFE031 delivers high performance and is designed to work with a
minimum number of external components. Consisting of a variety of functional and configurable blocks, the
AFE031 simplifies design efforts and reduces the time to market of many applications.
The AFE031 includes three primary functional blocks:
• Power Amplifier (PA)
• Transmitter (Tx)
• Receiver (Rx)
The AFE031 also consists of other support circuitry blocks that provide zero crossing detection, an additional
two-wire communications channel, and power-saving biasing blocks (see the Functional Block Diagram). All of
these functional blocks are digitally controlled by the microcontroller through the serial interface (SPI).
Figure 24 shows a typical powerline communications application system diagram. Table 1 is a complete list of
the sections within the AFE031.
Figure 24. Typical Powerline Communications System Diagram
Table 1. Block Descriptions
BLOCK DESCRIPTION
PA The PA block includes the power amplifier and associated pedestal biasing circuitry
Tx The Tx block includes the Tx_Filter and the Tx_PGA
Rx The Rx block includes the Rx PGA1, the Rx Filter, and the Rx PGA2
ERx The ER block includes the two-wire receiver
ETx The ER block includes the two-wire transmitter
DAC The DAC block includes a digital-to-analog converter
ZC The ZC block includes both zero crossing detectors
REF1 The REF1 block includes the internal bias generator for the PA block
The REF2 block includes the internal bias generators for the Tx, Rx, ERx, and ETx
REF2 blocks
20 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
RSET
+
100 nF47 Fm
PA Supply
CIN
PA_VS1 PA_VS2 T_SENSE
PA_OUT1
PA_OUT2
PA_ISETPA_GND1PA_GND1
PA_IN
Power
Amplifier
Inside the AFE031
PA_VS1 PA_VS2 T_SENSE
PA_OUT1
PA_OUT2
PA_ISETPA_GND1PA_GND1
PA_IN
Power
Amplifier
Inside the AFE031
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
BLOCK DESCRIPTIONS
PA Block
The Power Amplifier (PA) block consists of a high slew rate, high-voltage, and high-current operational amplifier.
The PA is configured with an inverting gain of 6.5 V/V, has a low-pass filter response, and maintains excellent
linearity and low distortion. The PA is specified to operate from 7 V to 24 V and can deliver up to ±1.5 A of
continuous output current over the specified junction temperature range of –40°C to +125°C. Figure 25 illustrates
the PA block.
Figure 25. PA Block Equivalent Circuit
Connecting the PA in a typical PLC application requires only two additional components: an ac coupling
capacitor, CIN, and the current limit programming resistor, RSET.Figure 26 shows the typical connections to the
PA block.
Figure 26. Typical Connections to the PA
Copyright © 2010–2012, Texas Instruments Incorporated 21
Product Folder Link(s): AFE031
R = 20 k
SET W·-5 kW
1.2 V
ILIM
(
(
1
(2 f )pHP
· · W ·20 k
C =
IN
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
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The external capacitor, CIN, introduces a single-pole, high-pass characteristic to the PA transfer function;
combined with the inherent low-pass transfer function, this characteristic results in a passband response. The
value of the high-pass cutoff frequency is determined by CIN reacting with the input resistance of the PA circuit,
and can be found from Equation 1:
(1)
Where:
• CIN = external input capacitor
• fHP = desired high-pass cutoff frequency
For example, setting CIN to 3.3 nF results in a high-pass cutoff frequency of 2.4 kHz. The voltage rating for CIN
should be determined to withstand operation up to the PA power-supply voltage.
When the transmitter is not in use, the output can be disabled and placed into a high-impedance state by writing
a '0' to the PA-OUT bit in the Enable2 Register. Additional power savings can be realized by shutting down the
PA when not in use. Shutting down the PA for power savings is accomplished by writing a '0' to the PA bit in the
Enable1 Register. Shutting down the PA also results in the PA output entering a high-impedance state. When the
PA shuts down, it consumes only 2 mW of power.
The PA_ISET pin (pin 46) provides a resistor-programmable output current limit for the PA block. Equation 2
determines the value of the external RSET resistor attached to this pin.
(2)
Where:
• RSET = the value of the external resistor connected between pin 46 and ground.
• ILIM = the value of the desired current limit for the PA.
Note that to ensure proper design margin with respect to manufacturing and temperature variations, a 30%
decrease of the value used in Equation 2 for ILIM over the nominal value of ILIM is recommended. See Figure 20,
PA Current Limit vs RSET.
Tx Block
The Tx block consists of the Tx PGA and Tx Filter. The Tx PGA is a low-noise, high-performance, programmable
gain amplifier. In DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the
Tx PGA operates as the internal digital-to-analog converter (DAC) output buffer with programmable gain. In
PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the Tx PGA operates
as a stand-alone programmable gain amplifier. The Tx PGA gain is programmed through the serial interface. The
Tx PGA gain settings are 0.25 V/V, 0.5 V/V, 0.707 V/V, and 1 V/V.
The Tx Filter is a unity-gain, fourth-order low-pass filter. The Tx Filter cutoff frequency is selectable between
CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD)
determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band;
setting Control1 Register bit location 3 to '1' selects CENELEC B, C, and D bands.
The AFE031 supports both DAC inputs or PWM inputs for the Tx signal path. DAC mode is recommended for
best performance. In DAC mode, no external components in the Tx signal path are required to meet regulatory
signal emissions requirements. When in DAC mode, the AFE031 accepts serial data from the microprocessor
and writes that data to the internal DAC registers. When in DAC mode (where pin 7 is a logical '1' and Enable1
Register bit location 5 is a logical '1'), the Tx PGA output must be directly coupled to the Tx_FIN1 input and the
unused Tx_FIN2 input must be grounded.
22 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
LPF
MCU
PGA PA
1
2 f 22 kp W
· · ·
C = Note (2)
Inside the AFE031
Tx_F_OUT Tx_PGA_
IN
Tx_F_IN1 PA_OUT1
PA_OUT2
Tx_PGA_
OUT
Tx_F_IN2
PA_IN
C
GPIO
Note (1)
DAC PGA LPF PA
SPI
MCU
1
2 f 22 kp W· · ·
C = Note (1)
Inside the AFE031
Tx_PGA_IN
Tx_PGA_
OUT
Tx_F_
IN1
PA_OUT1
PA_OUT2
SCLK
DIN
DOUT
CS
Tx_F_
OUT
Tx_F_
IN2 PA_IN
C
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
The proper connections for the Tx signal path for DAC mode operation are shown in Figure 27. Operating in
DAC mode results in the lowest distortion signal injected onto the ac mains. No additional external filtering
components are required to meet CENELEC requirements for A, B, C or D bands when operating in DAC mode.
(1) For capacitor value C,fis the desired lower cutoff frequency and 22 kΩis the PA input resistance.
Figure 27. Recommended Tx Signal Chain Connections Using DAC Mode
In PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the microprocessor
general-purpose input/output (GPIO) can be connected directly to either one of the Tx Filter inputs; the unused
input should remain unconnected. A lower distortion PWM signal generated from two PWM signals shifted in
phase by 90 degrees can be also be input to the Tx Filter through the use of both inputs. Figure 28 and
Figure 29 show the proper connections for single PWM and dual PWM operating modes, respectively.
(1) Leave unused Tx Filter input unconnected.
(2) For capacitor value C,fis the desired lower cutoff frequency and 22 kΩis the PA input resistance.
Figure 28. Recommended Tx Signal Chain Connections in PWM Mode Using One PWM Signal
Copyright © 2010–2012, Texas Instruments Incorporated 23
Product Folder Link(s): AFE031
C
LPF
MCU
PGA PA
1
2 f 22 kp W
· · ·
C = Note (3)
Tx_F_OUT Tx_PGA_
IN
Tx_F_IN1 PA_OUT1
PA_OUT2
Tx_PGA_
OUT
Tx_F_IN2
PA_IN
C
C
GPIO
Note (1)
Inside the AFE031
510 W510 W
Note (2)
LPF
MCU
PGA PA
1
2 f 22 kp W
· · ·
C = Note (2)
Inside the AFE031
Tx_F_OUT Tx_PGA_
IN
Tx_F_IN1 PA_OUT1
PA_OUT2
Tx_PGA_
OUT
Tx_F_IN2
PA_IN
C
GPIO
GPIO
Note (1)
43 kW
43 kW
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
(1) When using both Tx Filter inputs, use 43-kΩresistors to match the input resistance for best frequency response.
(2) For capacitor value C,fis the desired lower cutoff frequency and 22 kΩis the PA input resistance.
Figure 29. Recommended Tx Signal Chain Connections in PWM Mode Using Two PWM Signals
In PWM mode, there is inherently more distortion from the PWM signal than from the internal DAC. To achieve
the best results in PWM mode, add passive RC filters to increase the low-pass filtering. Figure 30 and Figure 31
illustrate the recommended locations of these RC filters.
(1) Leave unused Tx Filter input unconnected.
(2) Refer to Table 2.
(3) For capacitor value C,fis the desired lower cutoff frequency and 22 kΩis the PA input resistance.
Figure 30. Recommended Tx Signal Chain Connections in PWM Mode
Using One PWM Signal and Additional RC Filters
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Product Folder Link(s): AFE031
C
LPF PGA PA
1
2 f 22 kp W
· · ·
C = Note (3)
Tx_F_OUT Tx_PGA_
IN
PA_OUT1
PA_OUT2
Tx_PGA_
OUT PA_IN
C
C
Inside the AFE031
510 W510 W
Note (2)
MCU
Tx_F_IN1
Tx_F_IN2
GPIO
GPIO
Note (1)
43 kW
43 kW
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
(1) When using both Tx Filter inputs, use 43-kΩresistors to match the input resistance for best frequency response.
(2) Refer to Table 2.
(3) For capacitor value C,fis the desired lower cutoff frequency and 22 kΩis the PA input resistance.
Figure 31. Recommended Tx Signal Chain Connections in PWM Mode
Using Two PWM Signals and Additional RC Filters
For the capacitors listed in Table 2, it is recommended that these components be rated to withstand the full AVDD
power-supply voltage.
Table 2. Recommended External R and C Values to
Increase Tx Filter Response Order in PWM
Applications
FREQUENCY BAND R (Ω) C (nF)
SFSK: 63 kHz, 74 kHz 510 2.7
CENELEC A 510 1.5
CENELEC B, C, D 510 1
The Tx PGA and Tx Filter each have the inputs and outputs externally available in order to provide maximum
system design flexibility. Care should be taken when laying out the PCB traces from the inputs or outputs to
avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or from the outputs
to ground, less than 100 pF is recommended.
Rx Block
The Rx block consists of Rx PGA1, the Rx Filter, and Rx PGA2. Both Rx PGA1 and Rx PGA2 are high-
performance programmable gain amplifiers. Rx PGA1 can be configured through the SPI to operate as either an
attenuator or in gain. The gain steps of the Rx PGA1 are 0.25 V/V, 0.5 V/V, 1 V/V, and 2 V/V. The gain steps of
the Rx PGA2 are 1 V/V, 4 V/V, 16 V/V, and 64 V/V. Configuring the Rx PGA1 as an attenuator (at gains less
than 1 V/V) is useful for applications where the presence of large interference signals are present within the
signal band. Attenuating the large interference allows these signals to pass through the analog Rx signal chain
without causing an overload; the interference signal can then be processed and removed within the
microprocessor as necessary.
Copyright © 2010–2012, Texas Instruments Incorporated 25
Product Folder Link(s): AFE031
CC1
C2
R1
R2 1
2 fpR
· · · IN,PGA1
C =
L1
L2
From line coupling circuit To Rx PGA1
See Note (1)
C1
1
2 fpR
· · · IN,PGA2
C =
2
Rx C1 Rx C2
330 W
To ADC input on MCU
From line coupling circuit
or passive bandpass filter LPF
PGA PGA
Note (2)
Inside the AFE031
Rx_PGA1_OUT Rx_F_IN
Rx_PGA1_
IN
Rx_PGA2_
OUT
Rx_F_
OUT RX_PGA2_IN
C2
1
2 fpR
· · · IN,PGA1
C =
1Note (1)
Rx_C1 Rx_C2
See Note (3)
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
The Rx Filter is a very low noise, unity-gain, fourth-order low-pass filter. The Rx Filter cutoff frequency is
selectable between CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting
(CA CBCD) determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC
A band; setting Control1 Register bit location 3 to '1' selects the CENELEC B, C, and D bands. Because the Rx
Filter is a very low noise analog filter, two external capacitors are required to properly configure the Rx Filter.
Table 3 shows the proper capacitance values for CENELEC A, B, C, and D bands. Capacitor Rx C1 is connected
between pin 24 and ground, and Rx C2 is connected between pin 23 and ground. For the capacitors shown, it is
recommended that these components be rated to withstand the full AVDD power-supply voltage
Table 3. Recommended External Capacitors Required for Rx Filter
FREQUENCY BAND Rx C1, PIN 24 Rx C2, PIN 23 CUTOFF FREQUENCY (kHz)
CENELEC A 680 pF 680 pF 90
CENELEC B, C, D 270 pF 560 pF 145
Figure 32 illustrates the recommended connections for the Rx signal chain.
(1) For capacitor value C1,fis the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1.
(2) For capacitor value C2,fis the desired lower cutoff frequency and RIN,PGA2 is the input resistance of Rx PGA2.
(3) Refer to Table 3.
Figure 32. Recommended Connections for Rx Signal Chain
As Figure 33 shows, a fourth-order passive passband filter is optional but recommended for applications where
high performance is required. The external passive passband filter removes any unwanted, out-of-band signals
from the signal path, and prevents them from reaching the active internal filters within the AFE031.
(1) For capacitor value C,fis the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1. Refer
to Table 3.
Figure 33. Passive Bandpass Rx Filter
26 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
1
(2 f Zp1 C)
· · ·
C =
1
Z
(2 f
C
2
p)
· ·
L =
1
Z
(2 f
C
1
p)
· ·
L =
2
1
(2 f Zp2 C)· · ·
C =
2
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
The following steps can be used to quickly design the passive passband filter. (Note that these steps produce an
approximate result.)
1. Choose the filter characteristic impedance, ZC:
– For –6-db passband attenuation: R1= R2= ZC
– For 0-db passband attenuation: R1= ZC, R2= 10 ●ZC
2. Calculate values for C1, C2, L1, and L2using the following equations:
Table 4 and Table 5 shows standard values for common applications.
Table 4. Recommended Component Values for Fourth-Order Passive Bandpass Filter (0-db Passband
Attenuation)
FREQUENCY CHARACTERISTIC
RANGE IMPEDANCE R1 R2 C1 C2 L1 L2
FREQUENCY BAND (kHz) (Ω) (Ω) (Ω) (nF) (nF) (μH) (μH)
CENELEC A 35 to 95 1k 1k 10k 4.7 1.5 1500 4700
CENELEC B, C, D 95 to 150 1k 1k 10k 1.7 1 1200 1500
SFSK 63 to 74 1k 1k 10k 2.7 2.2 2200 2200
Table 5. Recommended Component Values for Fourth-Order Passive Bandpass Filter (–6-db Passband
Attenuation)
FREQUENCY CHARACTERISTIC
RANGE IMPEDANCE R1 R2 C1 C2 L1 L2
FREQUENCY BAND (kHz) (Ω) (Ω) (Ω) (nF) (nF) (μH) (μH)
CENELEC A 35 to 95 1k 1k 1k 4.7 1.5 1500 4700
CENELEC B, C, D 95 to 150 1k 1k 1k 1.7 1 1200 1500
SFSK 63 to 74 1k 1k 1k 2.7 2.2 2200 2200
Copyright © 2010–2012, Texas Instruments Incorporated 27
Product Folder Link(s): AFE031
C3
C4
R2
R3
L1
L2
From line coupling
circuit
C1
1
2 fpR
· · · IN,PGA2
C =
2
Rx C1 Rx C2
330 W
To ADC
input on MCU
LPF
PGA PGA
Note (2)
Inside the AFE031
Rx_PGA1_OUT Rx_F_IN
Rx_PGA1_
IN
Rx_PGA2_
OUT
Rx_F_
OUT RX_PGA2_IN
C2
1
2 fpR
· · · IN,PGA1
C =
1
Note (1)
Rx_C1 Rx_C2
See Note (3)
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
The Rx PGA1, Rx Filter, and Rx PGA2 components have all inputs and outputs externally available to provide
maximum system design flexibility. Care should be taken when laying out the PCB traces from the inputs or
outputs to avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or
outputs to ground, below 100 pF is recommended.
Figure 34 shows the complete Rx signal path, including the optional passive passband filter.
(1) For capacitor value C1,fis the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1.
(2) For capacitor value C2,fis the desired lower cutoff frequency and RIN,PGA2 is the input resistance of Rx PGA2.
(3) Refer to Table 3.
Figure 34. Complete Rx Signal Path (with Optional Bandpass Filter)
DAC Block
The DAC block consists only of the 10-bit DAC. The use of the DAC is recommended for best performance. The
serial interface is used to write directly to the DAC registers when the DAC pin (pin 7) is driven high. Placing the
DAC pin into a high state configures the SPI for direct serial interface to the DAC. Use the following sequence to
write to the DAC:
• Set CS low.
• Set the DAC pin (pin 7) high.
• Write a 10-bit word to DIN. The DAC register is left-justified and truncates more than 10 bits.
• CS high updates the DAC.
Refer to Figure 35 for an illustration of this sequence.
28 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
CS
DAC
DIN
SCLK
Time
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
NOTE: Dashed lines indicate optional additional clocks (data are ignored).
Figure 35. Writing to the DAC Register
Table 6 lists the DAC Register configurations.
Table 6. DAC Registers
DAC PIN HIGH:
DAC REGISTER <15:0> LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
DAC<0> 0 -- W Truncated
DAC<1> 1 -- W Truncated
DAC<2> 2 -- W Truncated
DAC<3> 3 -- W Truncated
DAC<4> 4 -- W Truncated
DAC<5> 5 -- W Truncated
DAC<6> 6 -- W DAC bit 0 = DAC LSB
DAC<7> 7 -- W DAC bit 1
DAC<8> 8 -- W DAC bit 2
DAC<9> 9 -- W DAC bit 3
DAC<10> 10 -- W DAC bit 4
DAC<11> 11 -- W DAC bit 5
DAC<12> 12 -- W DAC bit 6
DAC<13> 13 -- W DAC bit 7
DAC<14> 14 -- W DAC bit 8
DAC<15> 15 -- W DAC bit 9 = DAC MSB
Copyright © 2010–2012, Texas Instruments Incorporated 29
Product Folder Link(s): AFE031
AVDD
2
External 1-nF
noise reduction capacitor
AVDD
R
R
AGND
Inside the AFE031
4 kW
biasInternal
REF2
External 1- F
noise reduction capacitor
m
PA_VS
R
R
PA_GND
Inside the AFE031
4 kW
PA_V
2
Sbias
Internal
REF1
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
REF1 and REF2 Blocks
The REF1 and REF2 blocks create midscale power-supply biasing points used internally to the AFE031. Each
reference divides its respective power-supply voltage in half with a precision resistive voltage divider. REF1
provides a PA_VS/2 voltage used for the PA, while REF2 provides an AVDD/2 voltage used for the Tx PGA, Tx
Filter, Rx PGA1, Rx Filter, and Rx PGA2. Each REF block has its output brought out to an external pin that can
be used for filtering and noise reduction. Figure 36 and Figure 37 show the proper connections of the external
noise-reducing capacitors. These capacitors are optional, but are recommended for best performance.
Figure 36. REF1 Functional Diagram
Figure 37. REF2 Functional Diagram
30 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
0.0
3.3
ZCOUT
Time (5 ms/div)
0 50 100
350
0
-350
120 VAC to 240 VAC
50 Hz to 60 Hz
+
330 kW330 kW330 kW
120 VAC
to 240 VAC
50/60 Hz
ZLLS410 or
equivalent
ZLLS410 or
equivalent
AVDD
3.3 V
ZCIN ZCOUT
AVDD
AGND
Zero
Crossing
Inside the AFE031
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
Zero Crossing Detector Block
The AFE031 includes two zero crossing detectors. Zero crossing detectors can be used to synchronize
communications signals to the ac line or sources of noise. Typically, in single-phase applications, only a single
zero crossing detector is used. In three-phase applications, both zero crossing detectors can be used; one
component detects phase A, and one detects phase B. Phase C zero crossings can then be inferred from the
data gathered from the other phases. Figure 38 shows the AFE031 configured for non-isolated zero crossing
detection.
Figure 38. Non-Isolated Zero Crossing Detection Using the AFE031
Non-isolated zero crossing waveforms are shown in Figure 39.
Figure 39. Non-Isolated Zero Crossing Waveforms
Copyright © 2010–2012, Texas Instruments Incorporated 31
Product Folder Link(s): AFE031
0.0
3.3
ZCOUT
Time (5 ms/div)
0 50 100
350
0
-350
120 VAC to 240 VAC
50 Hz to 60 Hz
+
120 VAC
to 240 VAC
50/60 Hz
PS2505-1A Opto Isolator
or equivalent
AVDD
3.3 V
ZCIN ZCOUT
AVDD
AGND
Zero
Crossing
Inside the AFE031
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
For maximum protection of the AFE031 against line transients, it is recommended to use Schottky diodes as
indicated in Figure 38. These diodes should limit the ZC_IN pins (pins 38 and 39) to within the maximum rating
of (AVDD + 0.4 V) and (AGND – 0.4 V). Some applications may require an isolated zero crossing detection circuit.
With a minimal amount of components, the AFE031 can be configured for isolated zero crossing detection, as
Figure 40 shows.
Figure 40. Isolated Zero Crossing Detection Using the AFE031
Isolated zero crossing waveforms are shown in Figure 41.
Figure 41. Isolated Zero Crossing Waveforms
32 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
0
20
40
-
-
Gain (dB)
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
High-pass cutoff determined by:
f =
HP
1
2 R Cp· ·
IN EXT
where:
R = Input resistance of ERx = 78 k
C = External capacitance
W
IN
EXT
Time (s)
E_Tx_Out
E_Tx_In
E_Tx_Clk
3.3
3.3
3.3
0
0
0
AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
ETx and ERx Blocks
The AFE031 contains a two-wire transmitter block, ETx, and a two-wire receiver block, ERx. These blocks
support communications that use amplitude shift keying (ASK) with on-off keying (OOK) modulation.
The ETx block is a gated driver that allows for transmission of a carrier input signal and modulating input signal.
For typical applications, a 50-kHz square wave carrier signal is applied to E_Tx_Clk while the modulating signal
is applied to E_Tx_In. The output (E_Tx_Out) is then in a high-impedance state when E_Tx_In is '1'. Figure 42
shows the relationship between E_Tx_Clk, E_Tx_In, and E_Tx_Out.
Figure 42. ETx Block Transfer Function
The ERx Block consists of a low-pass analog filter configured in an inverting gain of –4.5 db. This block, along
with an external capacitor, can be used to create a passband filter response as shown in Figure 43.
Figure 43. ERx Block Frequency Response
Copyright © 2010–2012, Texas Instruments Incorporated 33
Product Folder Link(s): AFE031
+ +
N1 N2
E_Tx_In
E_Tx_CLK
E_Tx_Out
E_Rx_In
E_Rx_Out
GND
GPIO
GPIO
GPIO
TMS320F28x
Flexible PLC
Software Engine
AFE031
Internal Configuration
Two-Wire Bus
CEXT
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
The E_Rx_Out pin can be directly connected to either an available analog-to-digital converter (ADC) input or
GPIO on the host microcontroller. Figure 44 illustrates a typical two-wire application for ETx and ERx.
Figure 44. Typical Two-Wire Application for ETx and ERx
34 Copyright © 2010–2012, Texas Instruments Incorporated
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AFE031
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SBOS531D –AUGUST 2010–REVISED MAY 2012
SERIAL INTERFACE
The AFE031 is controlled through a serial interface that allows read/write access to the control and data
registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted
out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid
host SPI communications protocol. Table 7 through Table 16 show the complete register information.
Table 7. Data Register
REGISTER ADDRESS DEFAULT FUNCTION
ENABLE1 0x01 0x00 Block enable or disable
GAIN SELECT 0x02 0x32 Rx and Tx gain select
ENABLE2 0x03 0x00 Block enable or disable
CONTROL1 0x04 0x00 Frequency select and calibration, Tx and Rx status
CONTROL2 0x05 0x01 Interrupt enable
RESET 0x09 0x00 Interrupt status and device reset
DIE_ID 0x0A 0x00 Die name
REVISION 0x0B 0x02 Die revision
Table 8. Command Register
LOCATION
BIT NAME (15 = MSB) R/W FUNCTION
ADDR8 8 W Register address bit
ADDR9 9 W Register address bit
ADDR10 10 W Register address bit
ADDR11 11 W Register address bit
ADDR12 12 W Register address bit
ADDR13 13 W Register address bit
ADDR14 14 W Register address bit
R/W 15 W Read/write: read = 1, write = 0
Table 9. Enable1 Register: Address 0x01
Default: 0x00
Enable1 Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to enable/disable the PA Block.
PA 0 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the Tx Block.
TX 1 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the Rx Block.
RX 2 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the ERx Block.
ERX 3 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the ETx Block.
ETX 4 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the DAC Block.
DAC 5 0 R/W 0 = DAC disabled; switch is connected to Tx_PGA_IN pin.
1 = DAC enabled; switch is connected to DAC output.
-- 6 0 -- Reserved
-- 7 0 -- Reserved
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Table 10. Gain Select Register: Address 0x02
Default: 0x32
Gain Select Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to set the gain of the Rx PGA1.
00 = 0.25 V/V
RX1G-0, 0, 1 0, 1 R/W 01 = 0.5 V/V
RX1G-1 10 = 1 V/V
11 = 2 V/V
This bit is used to set the gain of the Rx PGA2.
00 = 1 V/V
RX2G-0, 2, 3 0, 0 R/W 01 = 4 V/V
RX2G-1 10 = 16 V/V
11 = 64 V/V
This bit is used to set the gain of the Tx PGA.
00 = 0.25 V/V
TXG-0, 4, 5 1, 1 R/W 01 = 0.5 V/V
TXG-1 10 = 0.707 V/V
11 = 1 V/V
-- 6 0 -- Reserved
-- 7 0 -- Reserved
Table 11. Enable2 Register: Address 0x03
Default: 0x00
Enable2 Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to enable/disable the ZC Block.
ZC 0 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the REF1 Block.
REF1 1 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the REF2 Block.
REF2 2 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the PA output stage.
When the PA output stage is enabled it functions normally with a
low output impedance, capable of driving heavy loads.
PA_OUT 3 0 R/W When the PA output stage is disabled it is placed into a high
impedance state.
0 = disabled, 1 = enabled.
-- 4 0 -- Reserved
-- 5 0 -- Reserved
-- 6 0 -- Reserved
-- 7 0 -- Reserved
36 Copyright © 2010–2012, Texas Instruments Incorporated
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SBOS531D –AUGUST 2010–REVISED MAY 2012
Table 12. Control1 Register: Address 0x04
Default: 0x00
Control1 Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to enable/disable the TX calibration mode.
TX_CAL 0 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the RX calibration mode.
RX_CAL 1 0 R/W 0 = disabled, 1 = enabled.
This bit is used to enable/disable the TX PGA calibration mode.
TX_PGA_CAL 2 0 R/W 0 = disabled, 1 = enabled.
This bit is used to select the frequency response of the Tx Filter
and Rx Filter.
CA_CBCD 3 0 R/W 0 = CENELEC A
1 = CENELEC B, C, D
-- 4 0 -- Reserved
-- 5 0 -- Reserved
This bit is used to indicate the status of the Tx Block.
TX_FLAG 6 0 R 0 = Tx Block is not ready for transmission.
1 = Tx Block is ready for transmission.
This bit is used to indicate the status of the Rx Block.
RX_FLAG 7 0 R 0 = Rx Block is not ready for reception.
1 = Rx Block is ready for reception.
Table 13. Control2 Register: Address 0x05
Default: 0x01
Control2 Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
-- 0 0 -- Reserved
-- 1 0 -- Reserved
-- 2 0 -- Reserved
-- 3 0 -- Reserved
-- 4 0 -- Reserved
This bit is used to enable/disable the T_flag bit in the RESET
T_FLAG_EN 5 0 R/W Register.
0 = disabled, 1 = enabled.
This bit is used to enable/disable the I_flag bit in the RESET
I_FLAG_EN 6 0 R/W Register.
0 = disabled, 1 = enabled.
-- 7 X -- Reserved
Copyright © 2010–2012, Texas Instruments Incorporated 37
Product Folder Link(s): AFE031
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Table 14. RESET Register: Address 0x09
Default: 0x00
Reset Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
-- 0 0 -- Reserved
-- 1 0 -- Reserved
SOFTRST0, These bits are used to perform a software reset of the ENABLE1,
SOFTRST1, 2, 3, 4 0, 0, 0 W ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT
SOFTRST2 registers. Writing '101' to these registers performs a software reset.
This bit is used to indicate the status of a PA thermal overload.
0 = On read, indicates that no thermal overload has occurred since
the last reset.
T_FLAG 5 0 R/W 0 = On write, resets this bit.
1 = On read, indicates that a thermal overload has occurred since
the last reset. Remains latched until reset.
This bit is used to indicate the status of a PA output current
overload.
0 = On read indicates that no current overload has occurred since
I_FLAG 6 0 R/W the last reset.
0 = On write, resets this bit.
1 = On read indicates that a current overload has occurred since
the last reset. Remains latched until reset.
-- 7 0 -- Reserved
Table 15. DieID Register: Address 0x0A
Default: 0x00
DieID Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
DIE ID<0> 0 0 R The Die ID register is hard-wired.
DIE ID<1> 1 0 R The Die ID register is hard-wired.
DIE ID<2> 2 0 R The Die ID register is hard-wired.
DIE ID<3> 3 0 R The Die ID register is hard-wired.
DIE ID<4> 4 0 R The Die ID register is hard-wired.
DIE ID<5> 5 0 R The Die ID register is hard-wired.
DIE ID<6> 6 0 R The Die ID register is hard-wired.
DIE ID<7> 7 0 R The Die ID register is hard-wired.
Table 16. Revision Register: Address 0x0B
Default: 0x02
Revision Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
REVISION ID<0> 0 0 R The revision register is hard-wired.
REVISION ID<1> 1 1 R The revision register is hard-wired.
REVISION ID<2> 2 0 R The revision register is hard-wired.
REVISION ID<3> 3 0 R The revision register is hard-wired.
REVISION ID<4> 4 0 R The revision register is hard-wired.
REVISION ID<5> 5 0 R The revision register is hard-wired.
REVISION ID<6> 6 0 R The revision register is hard-wired.
REVISION ID<7> 7 0 R The revision register is hard-wired.
38 Copyright © 2010–2012, Texas Instruments Incorporated
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SBOS531D –AUGUST 2010–REVISED MAY 2012
POWER SUPPLIES
The AFE031 has two low-voltage analog power-supply pins and one low-voltage digital supply pin. Internally, the
two analog supply pins are connected to each other through back-to-back electrostatic discharge (ESD)
protection diodes. These pins must be connected to each other on the application printed circuit board (PCB). It
is also recommended to connect the digital supply pin and the two analog supply pins together on the PCB. Both
low-voltage analog ground pins are also connected internally through back-to-back ESD protection diodes. These
ground pins should also be connected to the digital ground pin on the PCB. It is recommended to bypass the
low-voltage power supplies with a parallel combination of a 10-μf and 100-nf capacitor. The PA block is biased
separately from a high-voltage, high-current supply.
Two PA power supply pins and two PA ground pins are available to provide a path for the high currents
associated with driving the low impedance of the ac mains. Connecting the two PA supply pins together is
recommended. It is also recommended to place a bypass capacitor of 47 μF to 100 μF in parellel with 100 nF as
close as possible to the AFE031. Care must be taken when routing the high current ground lines on the PCB to
avoid creating voltage drops in the PCB ground that may vary with changes in load current.
The AFE031 has many options to enable or disable the functional blocks to allow for flexible power-savings
modes. Table 17 shows the specific power supply that each functional block draws power from, as well as the
typical amount of power drawn from the associated power supplies for both the enabled and disabled states. For
additional information on power-supply requirements refer to Application Report SBOA130,Analog Front-End
Design for a Narrowband Power-Line Communications Modem Using the AFE031 (available for download at
www.ti.com).
Table 17. Power Consumption with Enable and Disable Times (Typical)
AVDD SUPPLY DVDD SUPPLY PA SUPPLY
BLOCK STATUS ENABLE TIME DISABLE TIME CURRENT CURRENT CURRENT
On 10 μs – – – 61 mA
PA Off – 10 μs – – 70 μA
On 10 μs – 3.7 mA – –
Tx Off – 10 μs 1 μA – –
On 10 μs – 5.3 mA – –
Rx Off – 10 μs 1 μA – –
On 10 μs – 900 μA – –
ERx Off – 10 μs 1 μA – –
On 10 μs – 1.2 mA – –
ETx Off – 10 μs 1 μA – –
On 10 μs – – 16 μA –
DAC Off – 10 μs – 1 μA –
On 10 μs – 25 μA – –
ZC Off – 10 μs 1 μA – –
On 10 μs – – – 26 μA
REF1 Off – 10 μs – – 8 μA
On 10 μs – 25 μA – –
REF2 Off – 10 μs 4 μA – –
Copyright © 2010–2012, Texas Instruments Incorporated 39
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SBOS531D –AUGUST 2010–REVISED MAY 2012
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PIN DESCRIPTIONS
DAC (Pin 7)
The DAC pin is used to configure the SPI to either read or write data to the Command and Data Registers, or to
write data to the DAC register. Setting the DAC pin high allows access to the DAC register. Setting the DAC pin
low allows access to the Command and Data Registers.
SD (Pin 8)
The Shutdown pin (SD) can be used to shut down the entire AFE031 for maximum power savings. When the SD
pin is low, normal operation of the AFE031 occurs. When the SD pin is high, all circuit blocks within the AFE031,
including the serial interface, are placed into the lowest-power operating modes. In this condition, the entire
AFE031 draws only 95 μA of current. All register contents at the time the AFE031 is placed into shutdown mode
are saved; upon re-enabling the AFE031, the register contents retain the respective saved values.
INT Pin (9)
The Interrupt pin (INT) can be used to signal the microprocessor of an unusual operating condition that results
from an anomaly on the ac mains. The INTpin can be triggered by two external circuit conditions, depending
upon the Enable Register settings. The AFE031 can be programmed to issue an interrupt on these conditions:
• Current Overload
• Thermal Overload
Current Overload
The maximum output current allowed from the Power Amplifier can be programmed with the external RSET
resistor connected between PA_ISET (pin 46) and ground. If a fault condition should occur and cause an
overcurrent event for the PA, the PA goes into current limit and the I_FLAG bit (location 6 in the RESET
Register) is set to a '1' if the I_Flag_EN bit (location 6 in the Control2 Register) is enabled. This configuration
results in an interrupt signal at the INT pin. The I_FLAG bit remains set to '1' even after the device returns to
normal operation. The I_FLAG bit remains at '1' until it is reset by the microprocessor.
If the I_FLAG_EN bit (location 6 in the Control2 Register) is disabled and a current overload condition occurs, the
PA goes into current-limit mode to protect the AFE031; however, the contents of the I_FLAG bit (location 6 in the
RESET Register) remain at the respective previous values (presumably '0' for normal operation), and the
AFE031 does not issue an interrupt at the INT pin.
Thermal Overload
The AFE031 contains internal protection circuitry that automatically disables the PA output stage if the junction
temperature exceeds +150°C. If a fault condition occurs that causes a thermal overload, and if the T_FLAG_EN
bit (location 5 in the Control2 Register) is enabled, the T_FLAG bit (location 5 in the RESET Register) is set to a
'1'. This configuration results in an interrupt signal at the INT pin. The AFE031 includes a thermal hysteresis and
allows the PA to resume normal operation when the junction temperature reduces to +135°C. The T_FLAG bit
remains set to a '1' even after the device returns to normal operation. The T_FLAG bit remains '1' until it is reset
by the microprocessor.
If the T_FLAG_EN bit (location 5 in the Control2 Register) is disabled and a thermal overload condition occurs,
the PA continues to go into thermal limit and protect the AFE031, but the contents of the T_FLAG bit (location 5
in the RESET Register) remain at the previous value (presumably '0' for normal operation), and the AFE031 does
not issue an interrupt at the INT pin.
Once an interrupt is signaled (that is, INT goes low), the contents of the I_FLAG and T_FLAG bits can be read
by the microprocessor to determine the type of interrupt that occurred. Using the Control2 Register, each
interrupt type (current or thermal) can be individually enabled or disabled, allowing full user customization of the
INT function. For proper operation of the interrupt pin it is recommended to configure the interrupt enable
registers in the Control2 Register by writing to bit locations 5, 6, and 7 following the information in Table 18 after
each time the AFE031 is powered on. Failure to properly configure bit locations 5, 6, and 7 after power on may
result in unexpected interrupt signals.
40 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
0.1 Fm10 kW
(typ)
10 kW
(typ)
10 kW
(typ)
10 kW
(typ)
TMP411
D+
D-
V+
1
8
7
6
4
5
3
2
GND
SCL
SDA
ALERT/THERM2
THERM
+3.3 V
SMBus
Controller
Over-Temperature
Fault
50 pF
50 W
TSENSE
AFE031
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
Table 18 lists the register contents associated with each interrupt condition.
Table 18. Register Contents to Configure the Interrupt Pin
CONTROL2 REGISTER CONTENTS:
DETERMINE INTERRUPT PIN FUNCTIONALITY
I_FLAG_EN T_FLAG_EN
(CURRENT (THERMAL
OVERLOAD) OVERLOAD)
FUNCTION D7 D6 D5
POR (default values) undefined 0 0
No interrupt 0 0 0
Interrupt on thermal overload only 0 0 1
Interrupt on current overload only 0 1 0
Interrupt on thermal or current 011
overload
TSENSE Pin (10)
The TSENSE pin is internally connected to the anode of a temperature-sensing diode located within the PA
output stage. Figure 45 shows a remote junction temperature sensor circuit that can be used to measure the
junction temperature of AFE031. Measuring the junction temperature of the AFE031 is optional and not required.
Figure 45. Interfacing the TMP411 to the AFE031
Tx_FLAG (Pin 47)
The Tx_FLAG pin is an open drain output that indicates the readiness of the Tx signal path for transmission.
When the Tx_FLAG pin is high, the transmit signal path is enabled and ready for transmission. When the
Tx_FLAG pin is low, the transmit path is not ready for transmission.
Rx_FLAG (Pin 48)
The Rx_FLAG pin is an open drain output that indicates the readiness of the Rx signal path for transmission.
When the Rx_FLAG pin is high, the transmit signal path is enabled and ready for transmission. When the
Rx_FLAG pin is low, the transmit path is not ready for transmission.
Copyright © 2010–2012, Texas Instruments Incorporated 41
Product Folder Link(s): AFE031
SPI SPI
LPF
LPF
Line Coupling Interface
C2000 MCU AFE031
PA
DAC PGA
PGA
PGA
Line Coupling Interface
C2000 MCU
SPI
LPF
AFE031
LPF
SPI
PA
DAC PGA
PGA
PGA
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
CALIBRATION MODES
The AFE031 can be configured for three different calibration modes: Tx Calibration, Rx Calibration, and Tx PGA
Calibration. Calibration values can be determined during the calibration process and stored in system memory. A
one-time calibration can be performed the first time that the system powers on; this calibration remains valid over
the full temperature range and operating life of the AFE031, independent of the number of power-on/power-off
cycles, as long as the calibration factors remain in the system memory. Calibration mode is accessed through the
Control1 Register. Note that calibration is not required.
Tx Calibration Mode
The Tx PGA + Tx Filter ac gain can be calibrated in Tx Calibration Mode. Figure 46 shows the signal path during
Tx Calibration mode.
Figure 46. Tx Calibration Mode Configuration
Rx Calibration Mode
The Tx PGA + Rx PGA1 + Rx Filter + Rx PGA2 ac gain can be calibrated in Rx Calibration mode. Figure 47
shows the signal path during Rx Calibration mode.
Figure 47. Rx Calibration Mode Configuration
42 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
LPF
Line Coupling Interface
C2000 MCU AFE031
LPF
SPI SPI
PA
DAC PGA
PGA
PGA
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
Tx PGA Calibration Mode
The Tx PGA ac gain can be calibrated in Tx PGA Calibration mode. Figure 48 shows the signal path during Tx
PGA Calibration mode.
Figure 48. Tx PGA Calibration Mode Configuration
BASIC CONFIGURATION
Figure 49 shows the AFE031 configured in a typical PLC analog front-end application. The schematic shows the
connections to the microprocessor and ac line. The values of the passive components in Figure 49 are suitable
for a single-phase powerline communications application in the CENELEC A band, connected to a 120-VAC or
240-VAC, 50-Hz or 60-Hz ac line.
Copyright © 2010–2012, Texas Instruments Incorporated 43
Product Folder Link(s): AFE031
C10
10 nF
C1
C2
R11
330 W
See Note (1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SPI
DAC
Registers
DAC
Tx
PGA
Tx
Filter
LPF LPF
Power
Amplifier
Rx
PGA2
Rx
PGA1
Rx
Filter
Two-Wire
Support
Circuitry
Tx
Rx LPF
Zero
Crossing
R3
33 kW
R4
10 kW
R5
10 kW
R1
33 kW
R2
33 kW
R6 through R9
10 k eachW
3.3 V
3.3 V
+15 V
3.3 V
3.3 V
3.3 V
GPIO
GPIO
SPI
SPI
SPI
SPI
GPIO
GPIO
GPIO
TMS320F28x
Flexible PLC
Software Engine
C12
1 Fm
C11
10 nF
C19
33 nF
C20
22 nF
L3
330 Hm
L2
15 Hm
L1
1 Hm
R14
150 W
R13
150 W
23 kHz to
105 kHz
Fourth-Order
Passive
Passband
Filter
R10
7.5 kW
C9
1 nF
C7
10 nF
C4
10 Fm
ADC IN
Test
Point
C3
10 Fm
C18
470 nF
+ +
N1 N2
1.5:1
See Note (2)
R12
4.7 W
C17
10 nF
D4
TVS
C6
10 Fm
Phase
Neutral
Line Coupling Circuit
C13
10 Fm
C5
10 FmC14
10 Fm
C15
10 FmC16
100 nF
D2
D3
D1
L4
470 Hm
C8
3.3 nF
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
(1) Recommended values for C1 and C2:
1. C1:
– CENELEC A: 680 pF
– CENELEC B, C, D: 270 pF
2. C2:
– CENELEC A: 680 pF
– CENELEC B, C, D: 560 pF
Figure 49. Typical Powerline Communications Modem Application
44 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
+ +
N1 N2
Phase
Neutral
Low-Voltage
Capacitor
High-Voltage
Capacitor
Power
Amplifier
MOV
TVS
PA
Power Supply
D2
D1
D3
AFE031
+ +
N1 N2
Phase
Neutral
Low-Voltage
Capacitor
High-Voltage
Capacitor L
Power
Amplifier
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
LINE-COUPLING CIRCUIT
The line-coupling circuit is one of the most critical circuits in a powerline modem. The line-coupling circuit has
two primary functions: first, to block the low-frequency signal of the mains (commonly 50 Hz or 60 Hz) from
damaging the low-voltage modem circuitry; second, to couple the modem signal to and from the ac mains. A
typical line-coupling circuit is shown in Figure 50.
Figure 50. Simplified Line Coupling Circuit
For additional information on line-coupling interfaces with the AFE031, refer to Application Report SBOA130,
Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031 (available
for download at www.ti.com).
CIRCUIT PROTECTION
Powerline communications are often located in operating environments that are harsh for electrical components
connected to the ac line. Noise or surges from electrical anomalies such as lightning, capacitor bank switching,
inductive switching, or other grid fault conditions can damage high-performance integrated circuits if they are not
properly protected. The AFE031 can survive even the harshest conditions if several recommendations are
followed.
First, dissipate as much of the electrical disturbance before it reaches the AFE031 with a multi-layer approach
using metal-oxide varistors (MOVs), transient voltage suppression diodes (TVSs), Schottky diodes, and a Zener
diode. Figure 51 shows the recommended strategy for transient overvoltage protection.
Figure 51. Transient Overvoltage Protection for AFE031
Note that the high-voltage coupling capacitor must be able to withstand pulses up to the clamping protection
provided by the MOV. A metalized polypropylene capacitor, such as the 474MKP275KA from Illinois Capacitor,
Inc., is rated for 50 Hz to 60 Hz, 250 VAC to 310 VAC, and can withstand 24 impulses of 2.5 kV.
Copyright © 2010–2012, Texas Instruments Incorporated 45
Product Folder Link(s): AFE031
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
Table 19 lists several recommended transient protection components.
Table 19. Recommended Transient Protection Devices
120 VAC, 60 Hz
COMPONENT DESCRIPTION MANUFACTURER MFR PART NO (OR EQUIVALENT)
D1 Zener diode Diodes, Inc. 1SMB59xxB(1)
D2, D3 Schottky diode Diodes, Inc. 1N5819HW
TVS Transient voltage suppressor Diodec Semiconductor P6SMBJxxC(2)
MOV Varistor LittleFuse TMOV20RP140E
HV Cap High-voltage capacitor Illinois Capacitor, Inc 474MKP275KA(3)
240 VAC, 50 Hz
COMPONENT DESCRIPTION MANUFACTURER MFR PART NO (OR EQUIVALENT)
D1 Zener diode Diodes, Inc. 1SMB59xxB(1)
D2, D3 Schottky diode Diodes, Inc. 1N5819HW
TVS Transient voltage suppressor Diodec Semiconductor P6SMBJxxC(2)
MOV Varistor LittleFuse TMOV20RP300E
HV Cap High-voltage capacitor Illinois Capacitor, Inc 474MKP275KA(3)
(1) Select the Zener breakdown voltage at the lowest available rating beyond the normal power-supply operating range.
(2) Select the TVS breakdown voltage at or slightly greater than (0.5 ●PA_VS).
(3) A common value for the high-voltage capacitor is 470 nF. Other values may be substituted depending on the requirements of the
application. Note that when making a substitution, it is important in terms of reliability that the capacitor be selected from the same
familiy or equivalent family of capacitors rated to withstand high-voltage surges.
THERMAL CONSIDERATIONS
In a typical powerline communications application, the AFE031 dissipates 2 W of power when transmitting into
the low impedance of the ac line. This amount of power dissipation can increase the junction temperature, which
in turn can lead to a thermal overload that results in signal transmission interruptions if the proper thermal design
of the PCB has not been performed. Proper management of heat flow from the AFE031 as well as good PCB
design and construction are required to ensure proper device temperature, maximize performance, and extend
device operating life.
The AFE031 is assembled into a 7-mm2x 7-mm2, 48-lead, QFN package. As Figure 52 shows, this QFN
package has a large area exposed thermal pad on the underside that is used to conduct heat away from the
AFE031 and into the underlying PCB.
Figure 52. QFN Package with Large Area Exposed Thermal Pad
Some heat is conducted from the silicon die surface through the plastic packaging material and is transferred into
the ambient environment. Because plastic is a relatively poor conductor of heat, however, this route is not the
primary thermal path for heat flow. Heat also flows across the silicon die surface to the bond pads, through the
wire bonds, into the package leads, and finally into the top layer of the PCB. While both of these paths for heat
flow are important, the majority (nearly 80%) of the heat flows downward, through the silicon die, into the
thermally-conductive die attach epoxy, and into the exposed thermal pad on the underside of the package (see
Figure 53). Minimizing the thermal resistance of this downward path to the ambient environment maximizes the
life and performance of the device.
46 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
AFE031
Less than 1%
~20%
~80%
~20%
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
Figure 53. Heat Flow in the QFN Package
The exposed thermal pad must be soldered to the PCB thermal pad. The thermal pad on the PCB should be the
same size as the exposed thermal pad on the underside of the QFN package. Refer to Application Report,
QFN/SON PCB Attachment, literature number SLUA271A, for recommendations on attaching the thermal pad to
the PCB. Figure 54 illustrates the direction of heat spreading into the PCB from the device.
Figure 54. Heat Spreading into PCB
The heat spreading into the PCB is maximized if the thermal path is uninterrupted. Best results are achieved if
the heat-spreading surfaces are filled with copper to the greatest extent possible, maximizing the percent area
covered on each layer. As an example, a thermally robust, multilayer PCB design may consist of four layers with
copper (Cu) coverage of 60% in the top layer, 85% and 90% in the inner layers, respectively, and 95% on the
bottom layer.
Copyright © 2010–2012, Texas Instruments Incorporated 47
Product Folder Link(s): AFE031
35
33
31
29
27
25
23
21
19
17
15
Thermal Resistance (°C/W)
0.5 1 1.5 2 2.5
Cu Thickness (oz)
Four-Layer PCB, PCB
Area = 4.32 in , 2 oz Cu
(Results are from thermal
simulations)
2
28
26
24
22
20
18
16
14
12
10
Thermal Resistance (°C/W)
246 8 10 12 14
PCB Area (in )
2
THERMAL RESISTANCE vs BOARD AREA
Four-Layer PCB, 2 oz Cu
(Results are from thermal
simulations)
1 2 3 4 5 678
Number of Layers
36
34
32
30
28
26
24
22
20
Thermal Resistance ( C/W)°
THERMAL RESISTANCE vs NUMBER OF PCB LAYERS
PCB Area = 3 in , 2 oz Cu
(Results are from thermal
simulations)
2
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
Increasing the number of layers in the PCB, using thicker copper, and increasing the PCB area are all factors
that improve the spread of heat. Figure 55 through Figure 57, respectively, show thermal resistance performance
as a function of each of these factors.
Figure 55. Thermal Resistance as a Function of the Number of Layers in the PCB
Figure 56. Thermal Resistance as a Function of PCB Area
Figure 57. Thermal Resistance as a Function of Copper Thickness
48 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
For additional information on thermal PCB design using exposed thermal pad packages, refer to Application
Report SBOA130,Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the
AFE031 and Application Report SLMA002E,PowerPAD™ Thermally-Enhanced Package (both available for
download at www.ti.com).
Powerline Communications Developer’s Kit
A PLC developer’s kit (TMDSPLCKIT-V3) is available to order at www.ti.com/plc. This kit offers complete
hardware and software solutions for introducing flexible, efficient, and reliable networking capabilities to a wide
variety of applications. With unique modular hardware architecture and flexible software framework, TI’s PLC
solutions are the only PLC-based technology capable of supporting multiple protocol standards and modulation
schemes with a single platform. This technology enables designers to leverage product lines across global
markets. The flexibility of the platform also allows developers to optimize hardware and software performance for
specific environmental operating conditions while simplifying end-to-end product design. Based on TI’s powerful
C2000™ microcontroller architecture and the AFE031, developers can select the correct blend of processing
capacity and peripherals to either add powerline communications to an existing design or implement a complete
application with PLC communications.
The C2000 Powerline Modem Developer's Kit enables easy development of software-based PLC modems. The
kit includes two PLC modems based on the C2000 TMS320F28069 controlCARD and the AFE031. The included
PLC SUITE software supports several communication techniques, including OFDM (PRIME/G3 and FlexOFDM)
and SFSK. The kit also includes onboard USB JTAG emulation and Code Composer Studio.
PACKAGING/MECHANICALS
Complete mechanical drawings and packaging information are appended to the end of this data sheet.
Copyright © 2010–2012, Texas Instruments Incorporated 49
Product Folder Link(s): AFE031
AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2012) to Revision D Page
• Updated Figure 32 .............................................................................................................................................................. 26
• Updated Figure 34 .............................................................................................................................................................. 28
Changes from Revision B (September 2011) to Revision C Page
• Changed transmit power amplifier operating range description in Description section ........................................................ 1
• Added cross-reference to footnote 2 to Output short-circuit parameter in Absolute Maximum Ratings table ..................... 2
• Changed Frequency Response, Passband frequency (B/C/D Modes) parameter minimum and typical specifications
in Electrical Characteristics: Receiver (Rx) ........................................................................................................................... 6
• Deleted Digital Outputs (INT, Tx_Flag, Rx_Flag), INT pin high,INT pin low,Tx_Flag high,Tx_Flag low,Rx_Flag
high, and Rx_Flag low parameter units from Electrical Characteristics: Digital ................................................................... 8
• Changed Digital Outputs (INT, Tx_Flag, Rx_Flag), Tx_Flag high,Tx_Flag low,Rx_Flag high, and Rx_Flag low
parameter specification descriptions in Electrical Characteristics: Digital ............................................................................ 8
• Changed Operating Supply Range, Power amplifier supply voltage parameter maximum specification in Electrical
Characteristics: Power Supply ............................................................................................................................................ 10
• Changed title of Figure 20 .................................................................................................................................................. 18
• Changed description of PA operating range in PA Block section ....................................................................................... 21
• Updated Equation 2 ............................................................................................................................................................ 22
• Changed proper design margin note in PA Block section .................................................................................................. 22
• Updated Figure 35 .............................................................................................................................................................. 29
• Changed description of REF1 and REF2 Blocks section ................................................................................................... 30
• Changed title of Table 9 ...................................................................................................................................................... 35
• Changed second paragraph of Power Supplies section ..................................................................................................... 39
50 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE031
PACKAGE OPTION ADDENDUM
www.ti.com 9-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
AFE031AIRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
AFE031AIRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
COMBOSOLAR ACTIVE 0 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
AFE031AIRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
AFE031AIRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AFE031AIRGZR VQFN RGZ 48 2500 367.0 367.0 38.0
AFE031AIRGZT VQFN RGZ 48 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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