PD - 97129A IRFR1018EPbF IRFU1018EPbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits HEXFET(R) Power MOSFET D G S Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited) D-Pak IRFR1018EPbF 60V 7.1m: 8.4m: 79A c 56A I-Pak IRFU1018EPbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25C Parameter Max. Units Continuous Drain Current, VGS @ 10V (Silicon Limited) 79c ID @ TC = 100C Continuous Drain Current, VGS @ 10V (Silicon Limited) 56c ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 56 IDM Pulsed Drain Current d 315 PD @TC = 25C Maximum Power Dissipation 110 W Linear Derating Factor 0.76 VGS Gate-to-Source Voltage 20 W/C V dv/dt TJ Peak Diode Recovery f 21 Operating Junction and -55 to + 175 TSTG Storage Temperature Range A V/ns C 300 Soldering Temperature, for 10 seconds (1.6mm from case) Avalanche Characteristics EAS (Thermally limited) Single Pulse Avalanche Energy e 88 IAR Avalanche Current d 47 A EAR Repetitive Avalanche Energy g 11 mJ mJ Thermal Resistance Typ. Max. RJC Symbol Junction-to-Case k Parameter --- 1.32 RJA Junction-to-Ambient (PCB Mount) jk --- 50 RJA Junction-to-Ambient k --- 110 Units C/W Notes through are on page 2 www.irf.com 1 4/21/09 IRFR/U1018EPbF Static @ TJ = 25C (unless otherwise specified) Symbol Parameter V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Typ. Max. Units 60 --- --- --- 0.073 --- --- 7.1 8.4 2.0 --- 4.0 --- --- 20 --- --- 250 --- --- 100 --- --- -100 Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 47A g V VDS = VGS, ID = 100A A VDS = 60V, VGS = 0V VDS = 48V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V Dynamic @ TJ = 25C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Qg Qgs Qgd Qsync Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) 110 --- --- --- --- --- 46 10 12 34 --- 69 --- --- --- RG(int) td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance --- 0.73 13 35 55 46 2290 270 130 390 630 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)h --- --- Effective Output Capacitance (Time Related)g S nC Conditions VDS = 50V, ID = 47A ID = 47A VDS = 30V VGS = 10V g ID = 47A, VDS =0V, VGS = 10V ns pF VDD = 39V ID = 47A RG = 10 VGS = 10V g VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 60V i VGS = 0V, VDS = 0V to 60V h Diode Characteristics Symbol Parameter Min. Typ. Max. Units IS Continuous Source Current --- --- 79c ISM (Body Diode) Pulsed Source Current --- --- 315 VSD trr (Body Diode)d Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 56A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.08mH RG = 25, IAS = 47A, VGS =10V. Part not recommended for use above this value. ISD 47A, di/dt 1668A/s, VDD V(BR)DSS, TJ 175C. 2 A Conditions MOSFET symbol showing the integral reverse D G S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 47A, VGS = 0V g VR = 51V, --- 26 39 ns TJ = 25C IF = 47A TJ = 125C --- 31 47 di/dt = 100A/s g --- 24 36 nC TJ = 25C TJ = 125C --- 35 53 --- 1.8 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ approximately 90C. www.irf.com IRFR/U1018EPbF 1000 1000 VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 100 BOTTOM 4.5V 10 VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 BOTTOM 4.5V 10 60s PULSE WIDTH 60s PULSE WIDTH Tj = 25C Tj = 175C 1 1 0.1 1 10 100 0.1 100 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 10 VDS, Drain-to-Source Voltage (V) 1000 100 TJ = 175C 10 TJ = 25C 1 VDS = 25V 60s PULSE WIDTH 0.1 ID = 47A VGS = 10V 2.0 1.5 1.0 0.5 2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100120140160180 VGS, Gate-to-Source Voltage (V) TJ , Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 4000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd VGS, Gate-to-Source Voltage (V) 16 Coss = Cds + Cgd 3000 C, Capacitance (pF) 1 VDS, Drain-to-Source Voltage (V) Ciss 2000 1000 Coss Crss 0 1 VDS = 48V VDS = 30V 12 VDS = 12V 8 4 0 10 100 VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com ID= 47A 0 10 20 30 40 50 60 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFR/U1018EPbF 10000 100 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 TJ = 175C 10 TJ = 25C 1 OPERATION IN THIS AREA LIMITED BY R DS (on) 1000 100 1msec 10 LIMITED BY PACKAGE 10msec 1 Tc = 25C Tj = 175C Single Pulse VGS = 0V 0.0 0.5 1.0 1.5 0.1 2.0 LIMITED BY PACKAGE ID, Drain Current (A) 60 40 20 0 75 100 125 150 175 V(BR)DSS, Drain-to-Source Breakdown Voltage (V) 80 50 10 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 25 1 VDS , Drain-toSource Voltage (V) VSD , Source-to-Drain Voltage (V) 80 Id = 5mA 75 70 65 60 -60 -40 -20 0 20 40 60 80 100120140160180 TC, Case Temperature (C) TJ , Temperature ( C ) Fig 10. Drain-to-Source Breakdown Voltage Fig 9. Maximum Drain Current vs. Case Temperature 400 EAS, Single Pulse Avalanche Energy (mJ) 0.8 0.6 Energy (J) DC 0.1 0.1 0.4 0.2 0.0 ID 5.3A 11A BOTTOM 47A 350 TOP 300 250 200 150 100 50 0 0 10 20 30 40 50 60 VDS, Drain-to-Source Voltage (V) 4 100sec Fig 11. Typical COSS Stored Energy 25 50 75 100 125 150 175 Starting TJ, Junction Temperature (C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRFR/U1018EPbF Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.1 J 0.05 0.02 0.01 R1 R1 J 1 R2 R2 R3 R3 R4 R4 C 2 1 3 2 4 3 Ci= i/Ri Ci i/Ri 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 4 Ri (C/W) 0.026741 0.28078 0.606685 0.406128 (sec) 0.000007 0.000091 0.000843 0.005884 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case Avalanche Current (A) 100 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 0.01 10 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 100 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 10% Duty Cycle ID = 47A 80 60 40 20 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (C) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFR/U1018EPbF 14 ID = 1.0A 4.0 ID = 1.0mA 12 IF = 32A VR = 51V 3.5 ID = 100A 10 TJ = 25C TJ = 125C ID = 250A 3.0 8 IRR (A) VGS(th) Gate threshold Voltage (V) 4.5 2.5 6 2.0 4 1.5 2 1.0 -75 -50 -25 0 25 50 75 0 100 125 150 175 0 200 TJ , Temperature ( C ) 600 800 1000 diF /dt (A/s) Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage vs. Temperature 14 320 12 IF = 47A VR = 51V 280 IF = 32A VR = 51V 10 TJ = 25C TJ = 125C 240 TJ = 25C TJ = 125C 200 8 QRR (A) IRR (A) 400 6 160 120 4 80 2 40 0 0 0 200 400 600 800 1000 0 200 diF /dt (A/s) 400 600 800 1000 diF /dt (A/s) Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt 320 IF = 47A VR = 51V TJ = 25C 280 240 TJ = 125C QRR (A) 200 160 120 80 40 0 0 200 400 600 800 1000 diF /dt (A/s) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFR/U1018EPbF Driver Gate Drive D.U.T + - - * RG * * * * D.U.T. ISD Waveform Reverse Recovery Current VDD ** P.W. Period *** + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test D= VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer - Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple 5% * Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel *** VGS = 5V for Logic Level Devices Fig 21. Diode Reverse Recovery Test Circuit for HEXFET(R) Power MOSFETs V(BR)DSS 15V D.U.T RG VGS 20V DRIVER L VDS tp + V - DD IAS tp A 0.01 I AS Fig 22a. Unclamped Inductive Test Circuit RD VDS Fig 22b. Unclamped Inductive Waveforms VDS 90% VGS D.U.T. RG + -VDD 10% VGS 10V Pulse Width 1 s Duty Factor 0.1 % td(on) Fig 23a. Switching Time Test Circuit td(off) tr tf Fig 23b. Switching Time Waveforms Id Vds Vgs L DUT 0 20K 1K VCC S Vgs(th) Qgodr Fig 24a. Gate Charge Test Circuit www.irf.com Qgd Qgs2 Qgs1 Fig 24b. Gate Charge Waveform 7 IRFR/U1018EPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 2001 IN T HE AS S EMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IF IER LOGO Note: "P" in as s embly line pos ition indicates "Lead-F ree" IRFR120 116A 12 34 AS S EMBLY LOT CODE DAT E CODE YEAR 1 = 2001 WEEK 16 LINE A "P" in as s embly line pos ition indicates "Lead-F ree" qualification to the cons umer-level OR INT ERNAT IONAL RECT IF IER LOGO PART NUMBER IRFR120 12 AS S EMBLY LOT CODE 34 DAT E CODE P = DES IGNAT ES LEAD-F REE PRODUCT (OPT IONAL) P = DES IGNAT ES LEAD-F REE PRODUCT QUALIF IED T O T HE CONS UMER LEVEL (OPT IONAL) YEAR 1 = 2001 WEEK 16 A = AS S EMBLY S IT E CODE Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ 8 www.irf.com IRFR/U1018EPbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU120 WITH AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 2001 IN T HE AS S EMBLY LINE "A" INT ERNAT IONAL RECTIFIER LOGO PART NUMBER IRFU120 119A 56 78 AS S EMBLY LOT CODE Note: "P" in as s embly line pos ition indicates Lead-Free" DATE CODE YEAR 1 = 2001 WEEK 19 LINE A OR INT ERNAT IONAL RECTIFIER LOGO PART NUMBER IRFU120 56 AS S EMBLY LOT CODE 78 DATE CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 1 = 2001 WEEK 19 A = AS S EMBLY S ITE CODE Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ www.irf.com 9 IRFR/U1018EPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. This product has been designed for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.4/09 10 www.irf.com