IRFR1018EPBF - INFINEON TECHNOLOGIES AG

4/21/09

Benefits

lImproved Gate, Avalanche and Dynamic

dv/dt Ruggedness

lFully Characterized Capacitance and

Avalanche SOA

lEnhanced body diode dV/dt and dI/dt

Capability

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Applications

l High Efficiency Synchronous Rectification in

SMPS

l Uninterruptible Power Supply

l High Speed Power Switching

l Hard Switched and High Frequency Circuits

HEXFET® Power MOSFET

PD - 97129A

GDS

Gate Drain Source

IRFR1018EPbF

IRFU1018EPbF

Notes  through  are on page 2

D-Pak

IRFR1018EPbF

I-Pak

IRFU1018EPbF

VDSS 60V

RDS

(

)

typ. 7.1m:

max. 8.4m:

(

Silicon Limited

)

79A c

(

Packa

e Limited

)

56A

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) A

IDM Pulsed Drain Current d

PD @TC = 25°C Maximum Power Dissipation W

Linear Derating Factor W/°C

VGS Gate-to-Source Voltage V

dv/dt Peak Diode Recovery fV/ns

TJ Operating Junction and °C

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Avalanche Characteristics

EAS (Thermally limited) Single Pulse Avalanche Energy emJ

IAR Avalanche Current dA

EAR Repetitive Avalanche Energy gmJ

Thermal Resistance

Symbol Parameter Typ. Max. Units

RθJC Junction-to-Case k––– 1.32

RθJA Junction-to-Ambient (PCB Mount) jk ––– 50

RθJA Junction-to-Ambient k––– 110

56c

110

-55 to + 175

± 20

0.76

°C/W

300

Max.

79c

315

IRFR/U1018EPbF

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Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 56A. Note that current

limitations arising from heating of the device leads may occur with

some lead mounting arrangements.

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by TJmax, starting TJ = 25°C, L = 0.08mH

RG = 25Ω, IAS = 47A, VGS =10V. Part not recommended for

use above this value.

ISD ≤ 47A, di/dt ≤ 1668A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.

 Pulse width ≤ 400μs; duty cycle ≤ 2%.

 Coss eff. (TR) is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS.

 Coss eff. (ER) is a fixed capacitance that gives the same energy as

Coss while VDS is rising from 0 to 80% VDSS.

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 Rθ is measured at TJ approximately 90°C.

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V(BR)DSS Drain-to-Source Breakdown Voltage 60 ––– ––– V

ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.073 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 7.1 8.4 mΩ

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V

IDSS Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250

IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 110 ––– ––– S

QgTotal Gate Charge ––– 46 69 nC

Qgs Gate-to-Source Charge ––– 10 –––

Qgd Gate-to-Drain ("Miller") Charge ––– 12 –––

Qsync Total Gate Charge Sync. (Qg - Qgd)––– 34 –––

RG(int) Internal Gate Resistance ––– 0.73 ––– Ω

td(on) Turn-On Delay Time ––– 13 ––– ns

trRise Time ––– 35 –––

td(off) Turn-Off Delay Time ––– 55 –––

tfFall Time ––– 46 –––

Ciss Input Capacitance ––– 2290 –––

Coss Output Capacitance ––– 270 –––

Crss Reverse Transfer Capacitance ––– 130 ––– pF

Coss eff. (ER) Effective Output Capacitance (Energy Related)

––– 390 –––

Coss eff. (TR) Effective Output Capacitance (Time Related)g––– 630 –––

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

ISContinuous Source Current ––– ––– 79cA

(Body Diode)

ISM Pulsed Source Current ––– ––– 315

(Body Diode)d

VSD Diode Forward Voltage ––– ––– 1.3 V

trr Reverse Recovery Time ––– 26 39 ns TJ = 25°C VR = 51V,

––– 31 47 TJ = 125°C IF = 47A

Qrr Reverse Recovery Charge ––– 24 36 nC TJ = 25°C di/dt = 100A/μs g

––– 35 53 TJ = 125°C

IRRM Reverse Recovery Current ––– 1.8 ––– A TJ = 25°C

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

ID = 47A

RG = 10Ω

VGS = 10V g

VDD = 39V

ID = 47A, VDS =0V, VGS = 10V

TJ = 25°C, IS = 47A, VGS = 0V g

integral reverse

p-n junction diode.

Conditions

VGS = 0V, ID = 250μA

Reference to 25°C, ID = 5mAd

VGS = 10V, ID = 47A g

VDS = VGS, ID = 100μA

VDS = 60V, VGS = 0V

VDS = 48V, VGS = 0V, TJ = 125°C

MOSFET symbol

showing the

VDS = 30V

Conditions

VGS = 10V g

VGS = 0V

VDS = 50V

ƒ = 1.0MHz

VGS = 0V, VDS = 0V to 60V i

VGS = 0V, VDS = 0V to 60V h

Conditions

VDS = 50V, ID = 47A

ID = 47A

VGS = 20V

VGS = -20V

IRFR/U1018EPbF

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Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

Fig 2. Typical Output Characteristics

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

VGS

TOP 15V

10V

8.0V

6.0V

5.5V

5.0V

4.8V

BOTTOM 4.5V

≤60μs PULSE WIDTH

Tj = 25°C

4.5V

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

VGS

TOP 15V

10V

8.0V

6.0V

5.5V

5.0V

4.8V

BOTTOM 4.5V

≤60μs PULSE WIDTH

Tj = 175°C

4.5V

23456789

VGS, Gate-to-Source Voltage (V)

0.1

100

1000

ID, Drain-to-Source Current

(A)

TJ = 25°C

TJ = 175°C

VDS = 25V

≤60μs PULSE WIDTH

-60 -40 -20 020 40 60 80 100120140160180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 47A

VGS = 10V

110 100

VDS, Drain-to-Source Voltage (V)

1000

2000

3000

4000

C, Capacitance (pF)

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, Cds SHORTED

Crss = Cgd

Coss = Cds + Cgd

Coss

Crss

Ciss

0 102030405060

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 48V

VDS= 30V

VDS= 12V

ID= 47A

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Fig 8. Maximum Safe Operating Area

Fig 10. Drain-to-Source Breakdown Voltage

Fig 7. Typical Source-Drain Diode Forward Voltage

Fig 11. Typical COSS Stored Energy

Fig 9. Maximum Drain Current vs. Case Temperature

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

0.0 0.5 1.0 1.5 2.0

VSD, Source-to-Drain Voltage (V)

0.1

100

1000

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

010 20 30 40 50 60

VDS, Drain-to-Source Voltage (V)

0.0

0.2

0.4

0.6

0.8

Energy (μJ)

-60 -40 -20 020 40 60 80 100120140160180

TJ , Temperature ( °C )

V(BR)DSS, Drain-to-Source Breakdown Voltage (V)

Id = 5mA

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

100

150

200

250

300

350

400

EAS, Single Pulse Avalanche Energy (mJ)

I D

TOP 5.3A

11A

BOTTOM 47A

25 50 75 100 125 150 175

TC, Case Temperature (°C)

ID, Drain Current (A)

LIMITED BY PACKAGE

0.1 1 10 100

VDS, Drain-toSource Voltage (V)

0.1

100

1000

10000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY RDS(on)

100μsec

LIMITED BY PACKAGE

IRFR/U1018EPbF

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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 14. Typical Avalanche Current vs.Pulsewidth

Fig 15. Maximum Avalanche Energy vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. PD (ave) = Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. Iav = Allowable avalanche current.

7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as

25°C in Figure 14, 15).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

Thermal Response ( Z

thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE ) Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τι

(

sec

)

0.026741 0.000007

0.28078 0.000091

0.606685 0.000843

0.406128 0.005884

Ci= τi/Ri

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

100

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 10% Duty Cycle

ID = 47A

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

0.1

100

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔΤ j = 25°C and

Tstart = 150°C.

0.01

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

IRFR/U1018EPbF

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Fig. 17 - Typical Recovery Current vs. dif/dt

Fig 16. Threshold Voltage vs. Temperature

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

Fig. 20 - Typical Stored Charge vs. dif/dt

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

VGS(th) Gate threshold Voltage (V)

ID = 1.0A

ID = 1.0mA

ID = 250μA

ID = 100μA

0200 400 600 800 1000

diF /dt (A/μs)

IRR (A)

IF = 32A

VR = 51V

TJ = 25°C

TJ = 125°C

0200 400 600 800 1000

diF /dt (A/μs)

IRR (A)

IF = 47A

VR = 51V

TJ = 25°C

TJ = 125°C

0200 400 600 800 1000

diF /dt (A/μs)

120

160

200

240

280

320

QRR (A)

IF = 47A

VR = 51V

TJ = 25°C

TJ = 125°C

0200 400 600 800 1000

diF /dt (A/μs)

120

160

200

240

280

320

QRR (A)

IF = 32A

VR = 51V

TJ = 25°C

TJ = 125°C

IRFR/U1018EPbF

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Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms

VGS

VDS

90%

10%

td(on) td(off)

trtf

Fig 22b. Unclamped Inductive Waveforms

Fig 22a. Unclamped Inductive Test Circuit

(BR)DSS

0.01

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Vds

Vgs

Vgs(th)

Qgs1

Qgs2QgdQgodr

VCC

DUT

20K

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

=10V

Driver Gate Drive

D.U.T. I

Waveform

D.U.T. V

Waveform

Inductor Curent

D = P. W .

Period

*** VGS = 5V for Logic Level Devices

***







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



* Use P-Channel Driver for P-Channel Measurements

** Reverse Polarity for P-Channel

Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs

IRFR/U1018EPbF

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Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

D-Pak (TO-252AA) Part Marking Information

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

INTE RNATIONAL

ASS EMBLE D ON WW 16, 2001

IN THE ASSEMBLY LINE "A"

Note: "P" in as s embly line pos ition

EXAMPLE:

LOT CODE 1234

THIS IS AN IRFR120

WITH ASSEMBLY

i ndicates "L ead- F ree"

PRODUCT (OPTIONAL)

P = DE S I GNAT E S L E AD- F R E E

A = ASSEMBLY SITE CODE

PART NUMBER

WE E K 16

DAT E CODE

YEAR 1 = 2001

RECTIFIER

INTE RNATIONAL

LOGO

LOT CODE

ASSEMBLY

3412

IRFR120

116A

LINE A

RECTIFIER

LOGO

IRFR120

AS S E MB L Y

LOT CODE

YEAR 1 = 2001

DAT E CODE

PART NUMBER

WE E K 16

"P" in ass embly line position indicates

"L ead- F r ee" quali fi cation to the cons umer -level

P = DE S I GNAT E S L E AD- F R E E

PRODUCT QUALIFIED TO T HE

CONSUMER LEVEL (OPTIONAL)

IRFR/U1018EPbF

www.irf.com 9

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

LINE A

LOGO

INTERNAT IONAL

RECTIFIER

PRODUCT (OPT IONAL)

P = DES IGNAT ES LEAD-FREE

A = ASSEMBLY SITE CODE

IRFU120

PART NUMBER

WEEK 19

DAT E CODE

YEAR 1 = 2001

RECTIFIER

INTERNAT IONAL

LOGO

ASSEMBLY

LOT CODE

IRF U120

DAT E CODE

PART NUMBER

LOT CODE

ASSEMBLY

56 78

YEAR 1 = 2001

WEEK 19

119A

indicates Lead-Free"

AS SEMBLED ON WW 19, 2001

IN THE ASSEMBLY LINE "A"

Note: "P" in assembly line position

EXAMPLE:

WITH ASSEMBLY

THIS IS AN IRFU120

LOT CODE 5678

IRFR/U1018EPbF

10 www.irf.com

Data and specifications subject to change without notice.

This product has been designed for the Industrial market.

Qualification Standards can be found on IR’s Web site.

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

16.3 ( .641 )

15.7 ( .619 )

8.1 ( .318 )

7.9 ( .312 )

12.1 ( .476 )

11.9 ( .469 ) FEED DIRECTION FEED DIRECTION

16.3 ( .641 )

15.7 ( .619 )

TRR TRL

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

16 mm

13 INCH

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.4/09