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CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

VIN

VOUT+

VOUT±

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D±

VDD

GND

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LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

LM27403 Synchronous Buck Controller With Temperature-Compensated, Inductor-DCR-

Based Overcurrent Protection and Programmable Thermal Shutdown

1 Features 2 Applications

1• Up to 97% Efficiency and 93% Duty Cycle • DC-DC Converters and POL Modules

• Wide Input Voltage Range of 3 V to 20 V • Telecommunications Infrastructure

• Switching Frequency From 200 kHz to 1.2 MHz • Embedded Computing, Servers, Storage

• Inductor-DCR-Based Overcurrent Protection With 3 Description

Thermal Compensation The LM27403 is a feature-rich, easy-to-use,

• 0.6-V Reference With 1% Feedback Accuracy synchronous buck controller offering exceptional

• 30-ns Min On-Time for Low VOUT levels of integration and performance for superior

• Integrated High-Current MOSFET Drivers efficiency in high power density, point-of-load (POL)

DC-DC regulator solutions. The resistor-

– Adaptive Deadtime Control programmable switching frequency from 200 kHz to

• Ultrafast Line and Load Transient Response 1.2 MHz and integrated, high-current MOSFET gate

– High GBW Error Amplifier drivers with adaptive deadtime offer flexibility to

optimize solution size and maximize conversion

– PWM Line Feedforward efficiency.

• Integrated VDD Bias Supply LDO Subregulator High precision and low output voltage are easily

• Programmable System-Level OTP obtained with a 0.6-V, 1% accurate voltage reference

• Precision Enable With Hysteresis together with a 30-ns high-side MOSFET minimum

• Frequency Synchronization controllable on-time. Using lossless inductor dc

resistance (DCR) current sensing and an inexpensive

• Monotonic Prebiased Start-up 2N3904 BJT to sense temperature remotely at the

• Programmable Soft-Start With Tracking inductor, the LM27403 supports accurate and

• Output Remote Sense thermally compensated overcurrent protection (OCP).

• Open-Drain Power Good Indicator Device Information(1)

• 4-mm x 4-mm WQFN-24 PowerPAD™ Package PART NUMBER PACKAGE BODY SIZE (NOM)

LM27403 WQFN (24) 4.00 mm x 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

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Table of Contents

8.3 Feature Description................................................. 14

1 Features.................................................................. 18.4 Device Functional Modes........................................ 28

2 Applications ........................................................... 19 Application and Implementation ........................ 30

3 Description............................................................. 19.1 Application Information............................................ 30

4 Revision History..................................................... 29.2 Typical Applications ................................................ 37

5 Description (Continued)........................................ 310 Power Supply Recommendations ..................... 44

6 Pin Configuration and Functions......................... 311 Layout................................................................... 44

7 Specifications......................................................... 511.1 Layout Guidelines ................................................. 44

7.1 Absolute Maximum Ratings ...................................... 511.2 Layout Example .................................................... 47

7.2 Handling Ratings....................................................... 512 Device and Documentation Support................. 48

7.3 Recommended Operating Conditions....................... 512.1 Device Support .................................................... 48

7.4 Thermal Information.................................................. 612.2 Documentation Support ........................................ 48

7.5 Electrical Characteristics........................................... 612.3 Trademarks........................................................... 48

7.6 Typical Characteristics.............................................. 912.4 Electrostatic Discharge Caution............................ 48

8 Detailed Description............................................ 13 12.5 Glossary................................................................ 48

8.1 Overview................................................................. 13 13 Mechanical, Packaging, and Orderable

8.2 Functional Block Diagram....................................... 14 Information........................................................... 48

4 Revision History

Changes from Revision A (September 2013) to Revision B Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device

Functional Modes,Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ................................................................................................................................................................................... 1

Product Folder Links: LM27403

712

COMP

FADJ

SS/TRACK

UVLO/EN

SYNC

VIN

PGOOD

GND

CBOOT

VDD

D±

CS+

CS±

N.C.

OTP

D+

N.C.

PowerPADTM

LM27403

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SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

5 Description (Continued)

The LM27403 has a conventional voltage-mode control loop with high gain-bandwidth error amplifier and PWM

input voltage feedforward to simplify compensation design and enable excellent transient response throughout

the full line voltage and load current ranges. Forced-PWM (FPWM) operation eliminates frequency variation to

minimize EMI in sensitive applications. An open-drain Power Good circuit provides power-rail sequencing and

fault reporting. Other features include programmable system-level thermal shutdown with automatic recovery,

output voltage remote sense, configurable soft-start, monotonic start-up into prebiased loads, an integrated bias

supply low-dropout (LDO) regulator, external power supply tracking, precision enable with customizable

hysteresis for programmable line undervoltage lockout (UVLO), and synchronization capability for beat frequency

sensitive and multiregulator applications. The LM27403 is offered in a 4-mm x 4-mm thermally enhanced WQFN-

24 package with 0.5-mm pitch.

6 Pin Configuration and Functions

24-Pins

WQFN Package

(Top View)

Pin Functions

PIN I/O/P(1) DESCRIPTION

NAME NO.

High-side bootstrap connection. This pin is the high-side N-FET gate driver power supply. Connect a

CBOOT 18 P 100-nF ceramic capacitor between CBOOT and SW.

Compensation node output. This pin is an output voltage control-loop error amplifier output. COMP is

COMP 4 O connected to the FB pin through a compensation network to ensure stability.

Current-sense negative input. This pin is the inverting input to the current-sense comparator. 9.9 µA of

CS– 24 I nominal offset current at room temperature is provided to adjust the current limit setpoint.

CS+ 23 I Current-sense positive input. This pin is the noninverting input to the current-sense comparator.

(1) I=Input, O=Output, P=Power, G=Ground

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Pin Functions (continued)

PIN I/O/P(1) DESCRIPTION

NAME NO.

External temperature sense return. This pin is the return current path for the external NPN transistor

D– 10 I configured as a thermal diode. This trace should be routed as a differential pair with the D+ trace back

to the LM27403 to avoid excessive coupling from external noise sources. Connect D– to GND.

External temperature sense. A 2N3904-type NPN transistor configured as a remote thermal diode with

the base and collector shorted should be connected to this pin to sense the inductor temperature. The

D+ 9 I sensed temperature is used to compensate for the inductor DCR drift over temperature and to

implement system-level thermal shutdown protection.

Precision UVLO/enable input. To implement a VIN UVLO function, connect UVLO/EN to the tap of a

voltage divider between VIN and GND. UVLO/EN is initially pulled up by an internal 1.8-µA pullup

current source. UVLO/EN has both a 165-mV voltage hysteresis and an 8.7-µA pullup current

UVLO/EN 7 I hysteresis. Thus, when a rising UVLO/EN voltage exceeds the 1.15-V enable threshold, the internal

pullup current becomes 10.5 µA and the falling threshold voltage is 0.985 V. Therefore, the effective

total hysteresis can be customized to suit the specific application.

Exposed die attach pad. Connect this pad to the printed circuit board (PCB) ground plane using

EP — P multiple thermal vias.

Frequency adjust input. The switching frequency is programmable between 200 kHz and 1.2 MHz by

FADJ 5 I virtue of the size of resistor connected to this pin and GND.

Feedback input. This pin is a voltage-mode control-loop error amplifier inverting input to set the output

FB 3 I voltage. In closed-loop (output in regulation) operation, FB is at 0.6 V ±1%.

Common ground connection. This pin provides the power and signal return connections for analog

GND 13 G functions, including low-side MOSFET gate return, soft-start capacitor, OTP resistor, and frequency

adjust resistor.

HG 17 O High-side MOSFET gate drive output. This pin is the high-side N-FET gate connection.

LG 15 O Low-side MOSFET gate drive output. This pin is the low-side N-FET gate connection.

NC 19-22 G No connection. Connect directly to GND.

Overtemperature protection (OTP) output. A resistor and 0.1-µF capacitor from this pin to GND sets

the overtemperature protection setpoint for the DC-DC power supply solution using the temperature

OTP 8 I sensed at a remotely connected thermal diode. Connect this pin to GND if the system level OTP

function is not required.

Power Good monitor output. This open-drain output goes low during overcurrent, short-circuit, UVLO,

output overvoltage and undervoltage, overtemperature, or when the output is not regulated (such as an

PGOOD 11 O output prebias). An external pullup resistor to VDD or to an external rail is required. Included is a 20-µs

deglitch filter. The PGOOD voltage should not exceed 5.5 V.

Negative remote sense input. This pin eliminates the voltage drop between GND and the local ground

RS 2 I adjacent to the load. In particularly noisy environments, connect an RC filter between RS and GND.

Connect RS to GND at the IC if not used.

Soft-start or tracking input. This pin allows a predetermined startup rate to be defined with the use of a

SS/TRACK 1 I/O capacitor to GND. A 3-µA current source charges the capacitor until the reference reaches 0.6 V.

SS/TRACK can also be controlled with an external voltage source for tracking applications.

SW 16 P Power stage switch-node connection. This pin is the high-side N-FET gate driver return.

Synchronization input. This pin enables PLL synchronization to an external clock frequency. If a SYNC

SYNC 6 I signal is not present, the switching frequency defaults to the frequency set by the FADJ pin. This pin

should be tied to GND if not used.

Bias supply rail. This pin is a subregulated 4.7-V internal and gate drive bias supply rail. VDD also

supplies the current to CBOOT to facilitate high-side switching. Decouple VDD to GND locally with a

VDD 14 P 10-µF ceramic capacitor. VDD should not be used to drive auxiliary system loads because of gate

drive loading possibility.

Input voltage rail. This input is used to provide the feedforward modulation for output voltage control

VIN 12 P and for generating the internal bias supply voltage. Decouple VIN to GND locally with a 1-µF ceramic

capacitor. For better noise rejection, connect to the power stage input rail with an RC filter.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1).MIN MAX UNIT

VIN, CS+, CS–, SW(3)(4) –0.3 22 V

VDD, PGOOD –0.3 6 V

SS/TRACK, SYNC, FADJ, COMP, FB, RS –0.3 VVDD + 0.3 V

UVLO/EN –0.3 min (VVIN + 0.3, 6) V

Voltage(2) CBOOT(5) –0.3 24 V

CBOOT to SW –0.3 6 V

CS+ to CS– –1 1 V

OTP, D+, D– –0.3 VVDD V

Thermal Operating junction temperature, TJ–40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other condition beyond those included under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

(2) All voltages are with respect to the network ground pin unless otherwise noted.

(3) The SW pin can tolerate negative voltage spikes as low as –10 V and as high as 30 V for a duration up to 10 ns.

(4) Body diode of the low-side MOSFET notwithstanding, parasitic inductance in a real application may result in the SW voltage ringing

negative.

(5) The CBOOT pin can tolerate positive voltage spikes as high as 35 V for a duration up to 10 ns.

7.2 Handling Ratings MIN MAX UNIT

Tstg Storage temperature range –65 150 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2 2 kV

pins(1)

V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification –500 500 V

JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1).MIN NOM MAX UNIT

VIN tied to VDD 3.0 5.5 V

VIN Input voltage(2) VIN 3.0 20 V

SW SW pin voltage –0.3 20 V

VDD VDD pin voltage 2.6 4.7 5.5 V

PGOOD PGOOD pin voltage 0 5.5 V

UVLO/EN UVLO/EN pin voltage 0 min (VVIN, 5.5) V

SS/TRACK SS/TRACK pin voltage 0 VVDD V

SYNC SYNC pin voltage 0 5.5 V

RS RS pin voltage –0.1 0.1 V

TJOperating junction temperature –40 +125 °C

TAOperating free-air temperature –40 +125 °C

(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional but does not

guarantee performance limits.

(2) VDD is the output of the internal linear regulator bias supply. Under normal operating conditions, where VIN is greater than 5.5 V, VDD

must not be tied to any external voltage source. In an application where VIN is between 3.0 V and 5.5 V, connecting VIN to VDD

maximizes the bias supply rail voltage.

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7.4 Thermal Information LM27403

THERMAL METRIC(1) RTW UNIT

24 PINS

θJA Junction-to-ambient thermal resistance 32.7

θJCtop Junction-to-case (top) thermal resistance 31.2

θJB Junction-to-board thermal resistance 11.2 °C/W

ψJT Junction-to-top characterization parameter 0.2

ψJB Junction-to-board characterization parameter 11.2

θJCbot Junction-to-case (bottom) thermal resistance 1.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over –40°C to +125°C junction temperature

range unless otherwise stated(1),(2). VVIN = 12 V and all parameters at zero power dissipation (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OPERATIONAL SPECIFICATIONS

IQQuiescent current VFB = 0.6 V (not switching) 3.5 5.0 mA

IQ-SD Shutdown quiescent current VUVLO/EN = 0 V 25 45 µA

REFERENCE

VFB FB pin voltage accuracy 594 600 606 mV

IFB FB pin bias current VFB = 0.65 V –165 0 165 nA

INTERNAL UVLO

UVLO Input undervoltage lockout VVIN rising, VVDD rising 2.6 2.7 2.8 V

UVLO_hys UVLO hysteresis VVIN falling, VVDD falling 250 mV

SWITCHING

RFADJ = 4.12 kΩ925 1050 1150 kHz

FSW Switching frequency RFADJ = 20 kΩ435 500 555 kHz

RFADJ = 95.3 kΩ185 215 250 kHz

DMAX Maximum duty cycle FSW = 500 kHz 90% 93%

TOFF-MIN Minimum off-time VFB = 0.5 V, FSW = 500 kHz 110 150 190 ns

TON-MIN Minimum controllable on-time VFB = 0.7 V, FSW = 500 kHz 30 ns

VDD SUBREGULATOR AND BOOT

VDD Subregulator output voltage IVDD = 25 mA 4.2 4.7 5.3 V

VDDVDO Dropout voltage IVDD = 15 mA, VVIN = 3.0 V 150 mV

VDDCL VDD current limit VVDD = 4.0 V 106 mA

IQBOOT CBOOT pin leakage current VCBOOT – VSW = 4.5 V 0.5 nA

ERROR AMPLIFIER

BW-3dB Error amplifier open-loop bandwidth 6 MHz

AVOL Error amplifier dc gain 70 dB

ISOURCE COMP source current VFB = 0.5 V 1 mA

ISINK COMP sink current VFB = 0.7 V 100 µA

VCOMP-MAX Maximum COMP voltage VFB = 0.5 V 3.9 V

VCOMP-MIN Minimum COMP voltage VFB = 0.7 V 0.5 V

OVERCURRENT PROTECTION

Current limit comparator offset

VCS_OFFSET –3.5 0 3.5 mV

voltage

(1) All hot and cold limits are specified by correlating the electrical characteristic to process and temperature variations and applying

statistical process control.

(2) The junction temperature (TJin °C) is calculated from the ambient temperature (TAin °C) and power dissipation (PDin Watts) as follows:

TJ= TA+ (PD×θJA) where (°C/W) is the package thermal impedance provided in the Thermal Information section.

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SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Electrical Characteristics (continued)

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over –40°C to +125°C junction temperature

range unless otherwise stated(1),(2). VVIN = 12 V and all parameters at zero power dissipation (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCS– = 3 V, ΔVBE = 59.4 mV(3), TJ= 25°C 9.3 9.9 10.5 µA

ICS Current limit offset current VCS– = 3 V, D+ shorted to D– 3.4 5.0 6.6 µA

ICS-CV1 VVIN = 12 V 800 mV

ICS compliance voltage VVIN – VCS–,ΔICS < 5%

ICS-CV2 VVIN = 3 V 800 mV

ICS-TC ICS temperature coefficient Referenced to ΔVBE(4) 160 187 212 nA/mV

TCL-DELAY Current limit hiccup delay 5 ms

GATE DRIVERS

RDS(ON)1 IHG = 0.1 A (pullup) 1.5 Ω

High-side MOSFET driver on-state VCBOOT – VSW = 4.5 V

resistance

RDS(ON)2 IHG = –0.1 A (pulldown) 1.0 Ω

IDRV-HG-SRC Source current (pullup) 1.5 A

High-side MOSFET driver peak CLOAD = 3 nF

current

IDRV-HG-SINK Sink current (pulldown) 2.0 A

RDS(ON)3 ILG = 0.1 A (pullup) 1.5 Ω

Low-side MOSFET driver on-state VDD = 4.5 V

resistance

RDS(ON)4 ILG = –0.1 A (pulldown) 0.9 Ω

IDRV-LG-SRC Source current (pullup) 1.5 A

Low-side MOSFET driver peak CLOAD = 3 nF

current

IDRV-LG-SINK Sink current (pulldown) 2.0 A

TDEAD Adaptive dead-time 15 ns

SOFT-START

ISS Soft-start source current VSS/TRACK = 0 V 1.0 3.0 5.0 µA

ISS-PD Soft-start pulldown resistance VSS/TRACK = 0.6 V 330 Ω

TSS-INT Internal soft-start timeout 1.28 ms

POWER GOOD

IPGS PGOOD low sink current VPGOOD = 0.2 V, VFB = 0.75 V 70 100 µA

IPGL PGOOD leakage current VPGOOD = 5 V 1 10 µA

OVT Overvoltage threshold VFB rising, RS tied to GND 111% 116.5% 123%

OVTHYS OVT hysteresis VFB falling, RS tied to GND 3.5%

UVT Undervoltage threshold VFB rising, RS tied to GND 86% 91% 97%

UVTHYS UVT hysteresis VFB falling, RS tied to GND 4%

tdeglitch Deglitch time VPGOOD rising and falling 20 µs

UVLO/ENABLE

VUVLO1 Logic low threshold VUVLO/EN falling 0.94 0.985 1.03 V

VUVLO2 Logic high threshold VUVLO/EN rising 1.11 1.15 1.18 V

VUVLO-HYS UVLO/EN voltage hysteresis VUVLO/EN falling 139 165 190 mV

IUVLO1 UVLO/EN pullup current, disabled VUVLO/EN = 0 V 0.8 1.8 2.7 µA

IUVLO2 UVLO/EN pullup current, enabled VUVLO/EN = 1.25 V 5.5 10.5 15.5 µA

CLOCK SYNCHRONIZATION

VIH-SYNC SYNC pin VIH 2 V

VIL-SYNC SYNC pin VIL 0.8 V

SYNCFSW-L Minimum clock sync frequency 200 kHz

SYNCFSW-H Maximum clock sync frequency 1.2 MHz

SYNCISYNC pin input current 1 µA

EXTERNAL TEMPERATURE SENSE AND THERMAL SHUTDOWN

ID+1 D+ pin state 1 current 10 µA

ID+2 D+ pin state 2 current 100 µA

(3) The specified parameter is calculated based on a 2N3904 transistor at 25°C.

(4) Multiply by 19.9 to scale from nA/mV to ppm/°C (assumes 2N3904 BJT temperature sensor with ideality factor η=1.004).

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Electrical Characteristics (continued)

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over –40°C to +125°C junction temperature

range unless otherwise stated(1),(2). VVIN = 12 V and all parameters at zero power dissipation (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOTP Remote thermal current ΔVBE = 79.3 mV(5) 13.5 14.6 15.5 µA

IOTP-TC IOTP temperature coefficient Referenced to ΔVBE(4) 158 187 213 nA/mV

VTRIP Remote thermal trip point 1.15 V

Remote thermal trip point

VTRIP-HYS 80 mV

hysteresis ROTP(nom) = 80.7 kΩ,ΔVBE = 79.3 mV(5), TJ=

ROTP OTP resistance, thermal shutdown –5% 5%

125°C

TSHD Internal thermal shutdown threshold Rising 150 °C

Internal thermal shutdown threshold

TSHD-HYS 20 °C

hysteresis

(5) The specified parameter is calculated based on a 2N3904 transistor at 125°C.

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1.19

1.195

1.2

1.205

1.21

-50 -25 0 25 50 75 100 125

Output Voltage (V)

Temperature (C)

C005

3.5

3.6

3.7

3.8

3.9

-50 -25 0 25 50 75 100 125

Quiescent Current (mA)

Temperature (C)

C006

1.19

1.195

1.2

1.205

1.21

0 5 10 15 20 25

Output Voltage (V)

Output Current (A)

C003

1.19

1.195

1.2

1.205

1.21

0 2 4 6 8 10 12 14 16 18 20

Output Voltage (V)

Input Voltage (V)

C005

100

0 5 10 15 20 25

Efficiency (%)

Output Current (A)

VIN = 3.3V

VIN = 5V

VIN = 12V

VIN = 20V

C001

100

0 5 10 15 20 25

Efficiency (%)

Output Current (A)

VOUT = 0.8V

VOUT = 1.2V

VOUT = 1.8V

VOUT = 3.3V

VOUT = 5.3V

C002

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SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

7.6 Typical Characteristics

Unless otherwise stated, all datasheet curves were recorded using the circuit and powertrain designated in Figure 41 with

input and output voltages of 12 V and 1.2 V, respectively, and switching frequency of 250 kHz.

Figure 1. Efficiency Plot, VOUT = 1.2 V Figure 2. Efficiency Plot, VIN = 12 V

Figure 3. Load Regulation Figure 4. Line Regulation

Figure 5. Temperature Regulation Figure 6. Quiescent Current vs. Temperature, Nonswitching

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-50 -25 0 25 50 75 100 125

IOTP (PA)

Temperature (C)

C011

±50 ±25 0 25 50 75 100 125

ICS (µA)

Temperature (C)

C012

-50 -25 0 25 50 75 100 125

Deadtime (ns)

Temperature (C)

C009

4.5

4.55

4.6

4.65

4.7

4.75

4.8

-50 -25 0 25 50 75 100 125

VVDD (V)

Temperature (C)

C010

280

290

300

310

320

330

340

-50 -25 0 25 50 75 100 125

Switching Frequency (kHz)

Temperature (C)

C008

-50 -25 0 25 50 75 100 125

Shutdown Quiescent Current (PA)

Temperature (C)

C007

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Typical Characteristics (continued)

Unless otherwise stated, all datasheet curves were recorded using the circuit and powertrain designated in Figure 41 with

input and output voltages of 12 V and 1.2 V, respectively, and switching frequency of 250 kHz.

Figure 7. Shutdown Quiescent Current vs. Temperature Figure 8. Switching Frequency vs. Temperature

Figure 9. Deadtime vs. Temperature Figure 10. VDD Voltage vs. Temperature

Figure 11. OTP Current vs. Temperature Figure 12. CS– Current vs. Temperature

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VOUT

PGOOD

SS/TRACK

91% VOUT

EN to SS delay

UVLO/EN

VIN = 12 V

VOUT = 1.2 V

IOUT = 0 A

FSW = 300 kHz

VOUT

PGOOD

SS/TRACK

91% VOUT

EN to SS delay

UVLO/EN

VIN = 12 V

VOUT = 1.2 V

IOUT = 0 A

FSW = 300 kHz

100

200 400 600 800 1000 1200

RFADJ (k:)

Switching Frequency (kHz)

C015

VOUT

IOUT

VIN = 12 V

VOUT = 1.2 V

IOUT = 0 A ± 10 A ± 0 A

FSW = 300 kHz

0.0 0.2 0.4 0.6 0.8 1.0

ICS (PA)

VIN ± VCS- (V)

-40°C

25°C

125°C

C013

VOUT = 3.3V

28.2

28.4

28.6

28.8

-50 -25 0 25 50 75 100 125

Current Limit (A)

Temperature (C)

C014

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Typical Characteristics (continued)

Unless otherwise stated, all datasheet curves were recorded using the circuit and powertrain designated in Figure 41 with

input and output voltages of 12 V and 1.2 V, respectively, and switching frequency of 250 kHz.

Figure 13. CS– Current Source Compliance Voltage Figure 14. Current Limit Inception vs. Temperature

Figure 16. 10-A Step Load Transient Response, 2.5-A/µs

Figure 15. Switching Frequency vs. Frequency Adjust Slew Rate

Resistance

Figure 17. Start-up Characteristic Figure 18. Prebias Start-up Characteristic

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SYNC

VIN = 12 V

VOUT = 1.2 V

IOUT = 0 A

FSW = 500 kHz

VIN = 12 V

VOUT = 1.2 V

IOUT = 10 A

FSW = 500 kHz

Deadtime 1

LG off to HG on Deadtime 2

HG off to LG on

VOUT

UVLO/EN

SW IOUT

VIN = 12 V

VOUT = 1.2 V

IOUT = 7 A

FSW = 300 kHz

VOUT

IOUT

VIN = 12 V

VOUT = 1.2 V

FSW = 300 kHz

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Typical Characteristics (continued)

Unless otherwise stated, all datasheet curves were recorded using the circuit and powertrain designated in Figure 41 with

input and output voltages of 12 V and 1.2 V, respectively, and switching frequency of 250 kHz.

Figure 19. Shutdown Characteristic Figure 20. Current Limit Hiccup Mode

Figure 22. Switch Node Waveform

Figure 21. SYNC Waveform

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SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

8 Detailed Description

8.1 Overview

The distributed power supply architecture, pervasive in myriad applications including communications

infrastructure equipment and computing systems, uses an intermediate bus and multiple downstream DC-DC

regulators dedicated and proximate to each “point-of-load.” The ASICs, FPGAs, and microprocessors that

comprise these loads have supply voltage requirements whose levels are decreasing on an absolute basis and

whose tolerance bands are decreasing on a percentage basis. The hallmarks of point-of-load (POL) DC-DC

regulators are efficiency, size, load transient response, and cost.

To this end, the LM27403 is a feature-rich, easy-to-use, synchronous PWM DC-DC step-down controller capable

of providing an ultrahigh current output for demanding, high power density POL applications. An input voltage

range of 3 V to 20 V is compatible with a wide range of intermediate bus system rails and battery chemistries;

especially 3.3-V, 5-V, and 12-V inputs. The output voltage is adjustable from 0.6 V to as high as 93% of the input

voltage, with better than ±1% feedback system regulation accuracy over the full junction temperature range. With

an accurate, adjustable and thermally compensated inductor DCR based current limit setpoint, ferrite and

composite core inductors with low DCR and small footprint can be specified to maximize efficiency and reduce

power loss. High-current gate drivers with adaptive deadtime are used for the high-side and low-side MOSFETs

to provide further efficiency gains.

The LM27403 employs a voltage-mode control loop with output voltage remote sense, input voltage feedforward

modulation, and a high gain-bandwidth error amplifier to accurately regulate the output voltage over substantial

load, line, and temperature ranges. The switching frequency is programmable between 200 kHz and 1.2 MHz

through a resistor or an external synchronization signal. The LM27403 is available in a 4-mm × 4-mm, thermally

enhanced, 24-lead WQFN PowerPad package. This device offers high levels of integration by including MOSFET

gate drivers, a low dropout (LDO) bias supply linear regulator, and comprehensive fault protection features to

enable highly flexible, reliable, energy-efficient, and high power density regulator solutions.

Multiple fault conditions are accommodated, including overvoltage, undervoltage, overcurrent, and

overtemperature. To improve overcurrent setpoint accuracy and enable easier filter inductor selection, the

LM27403 thermally compensates for the temperature coefficient (TC) of the inductor's winding resistance by

sensing the inductor temperature with an external NPN transistor configured as a thermal diode. The same

thermal diode also monitors the PCB temperature to initiate a thermal shutdown in the event that the sensed

temperature exceeds the programmed thermal shutdown setpoint.

Product Folder Links: LM27403

UVLO/EN

VIN

2.7V VIN UVLO

4.73V

THERMAL

SHUTDOWN

VIN

VDD

2.7V

PLL & VCO

SYNC

FADJ

ENABLE

CLOCK

DIGITAL

SOFT-START

COUNTER

0.6V

REFERENCE

& LOGIC

SS/TRACK

VDD

3A

RAMP

VIN

PWM

ADAPTIVE DRIVER,

LEVEL SHIFTER

and

FAULT LOGIC

CS+

PGOOD

CS±

CBOOT

GND

VDD

699mV

678mV

546mV

522mV

COMP

VIN

HICCUP LOGIC

RESET

OCP

Comparator

VIN

1.8A

546mV +

VDD

UVLO

GND

KFF = 0.11

TEMPERATURE

MONITOR

VIN

D+

OTP

SWITCH = CLOSED

when VEN > 1.15V

VIN

8.7A

D±

3720 ppm/°C

Thermal

Coefficient

ICS IOTP

ICS

IOTP

1.15V

0.985V

1.15V

1.07V

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Input Range: VIN

The LM27403 operational input voltage range is from 3 V to 20 V. The device is intended for POL conversions

from 3.3-V, 5-V, and 12-V unregulated, semiregulated and fully regulated supply rails. It is also suitable for

connection to intermediate bus converters with output rails centered at 12 V and 9.6 V (derived from 4:1 and 5:1

primary-secondary transformer step-downs in nonregulated full-bridge converter topologies) and voltage levels

intrinsic to a wide variety of battery chemistries.

Product Folder Links: LM27403

7 8 9 10 11 12

24 23

CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

VIN

VOUT

GND

LM27403

VOUT

VIN VIN

D+

D±

VDD

COUT

CIN

CBOOT

RSCS

RISET

RCS

CCS

CVIN RVIN

RUV1

RUV2

RFADJ

RFB2

RC1

RC2

RFB1

ROTP

CC3

CC1

CVDD

COTP

DBOOT

DEN

CC2

CSS

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Feature Description (continued)

The LM27403 uses an internal LDO subregulator to provide a 4.7-V bias rail for the gate drive and control circuits

(assuming the input voltage is higher than 4.7 V plus the necessary subregulator dropout specification).

Naturally, it can be more favorable to connect VDD directly to the input during low input voltage operation (VVIN <

5.5 V). In summary, connecting VDD to VIN during low input voltage operation provides a greater gate drive

voltage level and thus an inherent efficiency benefit. However, by virtue of the low subregulator dropout voltage,

this VDD to VIN connection is not mandatory, thus enabling input ranges from 3 V up to 20 V. The application

circuits shown below detail LM27403 configuration options suitable for several input rails.

Figure 23. Schematic Diagram for VIN Operating Range of 3 V to 20 V

Figure 23 shows the schematic diagram for an input voltage ranging from 3 V to 20 V. Note that a finite

subregulator dropout voltage exists and is manifested to a larger extent when driving high gate charge (QG)

power MOSFETs at elevated switching frequencies. For example, at VVIN = 3 V, the VDD rail voltage is 2.8 V

with a dc operating current, IVDD, of 40 mA. Such a low gate drive rail may be insufficient to fully enhance the

power MOSFET gates. At the very least, MOSFET on-state resistance, RDS(ON), increases at such low gate drive

levels. Here are the main concerns when operating at a low input voltage:

• Increase of conduction losses (higher RDS(on) at lower VGS).

• Increase of switching losses associated with sluggish switching times when operating at low VGS levels.

• Deadtime may be larger as a result of the lower gate drive level and associated slower gate voltage slew rate.

This may become evident, for example, when using two high-side MOSFETs in a 3.3-V to 2.5-V converter

design.

• Dramatic reduction in the range of suitable MOSFETs that a designer can choose from (MOSFETs with

RDS(on) rated at VGS = 2.5 V become mandatory).

Note that the increased on-state resistance is compounded by an increase in MOSFET junction temperature,

bearing in mind the negative temperature coefficient of the MOSFET threshold voltage.

Product Folder Links: LM27403

7 8 9 10 11 12

24 23

CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

VIN

VOUT

GND

LM27403

VOUT

VIN

D+

D±

VDD

COUT

CIN

CBOOT

RSCS

RISET

RCS

CCS

CVIN RVIN

RFADJ

RFB2

RC1

RC2

RFB1

ROTP

CSS

CC3

CC1

CVDD

COTP

DBOOT

CC2

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Feature Description (continued)

In general, the subregulator is rated to drive the two internal gate driver stages in addition to the quiescent

current associated with LM27403 operation. Figure 24 shows the schematic diagram for lower input voltages

such as 3.0 V to 5.5 V. The LM27403's VDD and VIN pins can be tied together if the input voltage is guaranteed

not to exceed 5.5 V (absolute maximum 6 V). This short bypasses the internal LDO bias regulator and eliminates

the LDO dropout voltage and power dissipation. An RC filter from the input rail to the VIN pin, for example 2.2 Ω

and 1 µF, presents supplementary filtering at the VIN pin. Low gate threshold voltage MOSFETs are

recommended for this configuration.

Figure 24. Schematic Diagram for VIN Operating Range of 3.0 V to 5.5 V

8.3.2 Output Voltage: FB Voltage and Accuracy

The reference voltage seen at the FB pin is set at 0.6 V, and a feedback system accuracy of ±1% over the full

junction temperature range is met. Junction temperature range for the device is –40°C to +125°C. While

somewhat dependent on frequency and load current levels, the LM27403 is generally capable of providing output

voltages in the range of 0.6 V to a maximum of greater than 90% VIN. The dc output voltage during normal

operation is set by the feedback resistor network, RFB1 and RFB2, connected to VOUT.

8.3.3 Input and Bias Rail Voltages: VIN and VDD

The LM27403 internal UVLOs ensure that the input rail (VIN) and bias supply rail (VDD) are charged and stable

at 2.7 V before switching begins. VDD and VIN have independent UVLO comparators, each with 250 mV of

hysteresis. There is a definite delay between UVLO power-on and switching power-on. This delay is related to

the fact that the LM27403 does not begin switching until the internal temperature sense circuitry is ready and

stabilized. The delay is four measurement cycles on D+, equivalent to 512 clock cycles.

The VDD bias supply LDO has a nominal current limit of 106 mA during normal operation. However, a lower

current limit is engaged at startup to control the rate of rise of the VDD voltage. Figure 25 shows the typical

scope waveforms of VDD and VOUT when the input voltage is instantaneously applied. Here, the VDD voltage

ramps in approximately 1.4 ms based on a 10-µF VDD decoupling capacitor and current-limited VDD feature. For

more details, please see the LM27403 EVM User's Guide,SNVU233.

Product Folder Links: LM27403

VIN

8.7 A

1.8 A

1.15V

UVLO/EN

UVLO

Comparator

RUV1

RUV2

LM27403

0.985V

VIN

VOUT

VDD

VIN

VDD

startup time

VIN = 12 V

VOUT = 1.2 V

IOUT = 0 A

FSW = 300 kHz

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Feature Description (continued)

Figure 25. Typical Startup Waveforms of VDD and VOUT With Controlled Ramp Rates

8.3.4 Precision Enable: UVLO/EN

The UVLO/EN pin represents a precision analog enable function for user-defined UVLO power-on input voltage

levels and to toggle the output on and off. The UVLO/EN pin is essentially a comparator-based input referenced

to a flat bandgap voltage with a fixed hysteresis of 165 mV.

The UVLO/EN pin has an internal pullup current of 1.8 µA, as shown in Figure 26. There is also a low IQ

shutdown mode when UVLO/EN is effectively pulled below a base-emitter voltage drop (approximately 0.7 V at

room temperature). This mode shuts down the bias currents of the LM27403, but the UVLO/EN pullup current

source is still available. If UVLO/EN is pulled below this hard shutdown threshold, the internal LDO regulator

powers off and the VDD rail collapses.

Figure 26. Precision UVLO/Enable Circuit with Hysteretic Comparator and Pullup Current Sources

When the precision enable threshold of 1.15 V is exceeded, the UVLO/EN pullup current source increases from

1.8 µA to 10.5 µA (that is, an 8.7-µA hysteresis current). Use this feature to create a customizable UVLO

hysteresis (above the standard 165-mV fixed voltage hysteresis) based on the resistor divider from VIN to turn on

and off the LM27403 at the required input voltage levels. Also, use a capacitor from the UVLO/EN pin to GND to

implement a fixed time delay in power systems with timed sequencing requirements.

Product Folder Links: LM27403

FADJ 0.99

10000

R k 7

F kHz 100

: 

ª º

¬ ¼ 

ª º

¬ ¼

UVLO2

UV2 UV1 IN(on) UVLO2 UV1UVLO1

R R V V R I

 

UVLO1

IN(on) IN(off)

UVLO2

UV1 UVLO1

UVLO2 UVLO1 UVLO2

V V

I I V



UVLO/EN

VOUT

VUVLO-HYS

1.150V

0.985V

VUVLO2

VUVLO1 VIN 165mV

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Feature Description (continued)

Figure 27 shows an example using the circuit in Figure 23 where the input voltage is ramping from 0 V to 10 V in

100 ms. Here, the UVLO resistors, RUV1 and RUV2, are respectively set to 47.5 kΩand 10 kΩ. Given these

resistances, the typical input UVLO turn-on and turn-off levels are 6.5 V and 5.2 V, respectively. The UVLO/EN

pin voltage steps at the rising and falling thresholds are defined by the UVLO/EN pin current hysteresis.

Figure 27. Typical Input Voltage UVLO Turn On and Off Behavior

Given VIN(on) and VIN(off) as the input voltage turn-on and turn-off thresholds, respectively, select the UVLO

resistors using the following expressions:

(1)

(2)

The UVLO/EN pin has a maximum operating voltage rating equal to the input voltage or 5.5V, whichever is

lower. Do not exceed this rating. If the input UVLO level is set at low input voltage, it is possible that this

maximum UVLO/EN pin voltage could be exceeded at the higher end of the input voltage operating range. In this

case, use a small 4.7-V zener diode clamp, designated DEN in Figure 23, from UVLO/EN to GND, such that the

maximum operating level is never exceeded.

8.3.5 Switching Frequency

There are two options for setting the switching frequency of the LM27403, thus providing a power supply

designer a level of flexibility when choosing external components for multiple applications. To adjust the

frequency, use a resistor from the FADJ pin to GND, or synchronize the LM27403 to an external clock signal

through the SYNC pin.

8.3.5.1 Frequency Adjust: FADJ

Adjust the LM27403 free-running switching frequency by using a resistor from the FADJ pin to GND. The

switching frequency range of the device is from 200 kHz to 1.2 MHz. An open circuit at the FADJ pin forces the

frequency to the minimum value. FADJ shorted moves the frequency to its maximum value. The frequency set

resistance, RFADJ, is governed by Equation 3.

(3)

E96 resistors for common switching frequencies are given in Table 1.

Product Folder Links: LM27403

SYNC

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Table 1. Frequency Set Resistors

SWITCHING FREQUENCY FREQUENCY SET RESISTANCE

(kHz) (kΩ)

215 95.3

250 68.1

300 47.5

500 20

600 15

800 7.5

1050 4.12

1200 2.87

8.3.5.2 Clock Synchronization: SYNC

Apply an external clock synchronization signal to the LM27403 to synchronize switching in both frequency and

phase. Requirements for the clock SYNC signal are:

• Clock SYNC range: 200 kHz to 1.2 MHz

• SYNC frequency range from the FADJ frequency: up to 400 kHz (up only)

In applications where the external clock is not applied to the LM27403, use the external FADJ resistor to set the

minimum switching frequency. When the external clock is applied, it takes precedence only if the switching

frequency is greater than that set by the FADJ resistor. When the external clock is disconnected, the LM27403

switching frequency does not decrease below the minimum frequency set by the resistor. Setting a minimum

frequency in this way prevents the inductor ripple current from increasing dramatically. Externally tie SYNC to

GND if synchronization functionality is not required. The SYNC logic thresholds are based on an NMOS

threshold referenced to GND and, as such, are effectively independent of the VDD operating voltage.

Figure 28 shows a SYNC TTL signal at 600 kHz and the corresponding SW node waveform (VIN = 12 V, VOUT =

1.2 V, free-running frequency = 250 kHz). The synchronization is with respect to the rising edge of SYNC. The

rising edge of the SW voltage is phase delayed relative to SYNC by approximately 250 ns.

Figure 28. Typical 600-kHz SYNC Waveform

8.3.6 Temperature Sensing: D+ and D–

The LM27403 PWM controller offers low-cost programmable thermal protection by using remote thermal diode

temperature measurements based on the change in forward bias voltage of a diode when operated at two

different currents. The thermal diode is a discrete small-signal 2N3904 type silicon NPN BJT located (in good

thermal contact) adjacent the filter inductor.

Product Folder Links: LM27403

-40°C

25°C

125°C

ûVBE = 59.4 mV

ûVBE = 46.4 mV

ûVBE = 79.3 mV

( )

q V

T k ln 10

high

BE(high) BE(low )

low

V V ln

q I

æ ö

- = ç ÷

ç ÷

è ø

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

The ideality factor is a parameter in the diode I-V relationship that approaches 1.0 or 2.0 as carrier diffusion or

recombination current dominate current flow, respectively. The ideality factor for 2N3904 type diode-connected

BJTs available from several manufacturers is typically 1.004. Note that 3-terminal BJTs such as the 2N3904 are

vastly preferred over true 2-terminal diodes in this application. Discrete 2-terminal diodes with current largely

dictated by recombination have a much higher ideality factor (η= 1.2 to 1.5) than BJTs and, to such an extent,

would cause unacceptable temperature measurement error.

Switched capacitor technology is integrated in the LM27403 to sample and measure the base-emitter voltages

created by respective 10-µA and 100-µA bias currents flowing from the D+ to D– pins. The difference in these

voltages, termed ΔVBE, is readily extracted and the sensed temperature is calculated noting that ΔVBE is directly

proportional to temperature as follows:

where

• k = Boltzmann’s constant, 1.3806488 × 10-23J/K (Joules/Kelvin)

• T = absolute temperature in Kelvin (K)

• q = electron charge = 1.602176 x 10-19 C (Coulombs)

•η= diode ideality factor = 1.004

• Ilow = bias current in state 1 = 10 µA

• Ihigh = bias current in state 2 = 100 µA (4)

The source currents from the D+ pin during state 1 and state 2 are 10 µA and 100 µA, respectively. The sensed

temperature in Kelvin becomes:

(5)

Figure 29 shows the 2N3904 VBE voltage at ambient temperatures of –40°C, 25°C and 125°C. The low and high

states in VBE voltage correspond to the 10-µA and 100-µA currents sourced from D+, each of 64 clock cycle

duration. The voltage level is sampled at the end of each state. While the dc level of the VBE voltage decreases

logarithmically with increasing temperature, the ΔVBE amplitude increases with and is directly proportional to

temperature according to Equation 5.

Figure 29. Typical 2N3904 Base-Emitter Voltage at –40°C, 25°C and 125°C

Note that D– is essentially a kelvin connection to the remote thermal diode. As such, the D– pin needs to be tied

to GND at the LM27403; the D– trace should not connect to any of the PCBs current-carrying ground planes.

Product Folder Links: LM27403

OTP 398

R 80.7 k N

105 273



OTP OTP(125°C) OTP

398

R = R T (°C) + 273

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

8.3.7 Thermal Shutdown: OTP

A current proportional to the sensed temperature is sourced from the OTP pin. The resultant voltage at the OTP

pin (set by a resistor connected from OTP to GND) is compared to an internal shutdown threshold of 1.15 V with

80-mV hysteresis. When the threshold is exceeded, the device stops switching until the sensed temperature

drops to a level where the OTP pin voltage falls to the restart threshold. The external thermal protection is

disabled by grounding the OTP pin. The thermal shutdown setpoint is governed by Equation 6:

where

• ROTP is the required resistance at the OTP pin for the desired thermal shutdown temperature

• ROTP(125°C) is the nominal resistance at the OTP pin , 80.7 kΩ, for 125°C thermal shutdown, and

• TOTP is the desired thermal shutdown temperature. (6)

For example, the OTP resistor required for a thermal shutdown setpoint of 105°C is calculated as shown in

Equation 7:

(7)

A 100-nF capacitor connected in parallel with ROTP is required. When the IC detects an overtemperature event, it

responds with the normal hiccup-mode sequence of events when going into shutdown. More specifically, the

following steps occur when an internal or external OTP event is detected:

1. The high-side MOSFET immediately turns off.

2. An internal zero-cross circuit is enabled to detect whether the inductor current is positive or negative:

(a) If the current is negative, the low-side MOSFET immediately turns off.

(b) If the current is positive, the low-side MOSFET turns off when the inductor current ramps down to zero.

Note that it is important to prevent water-soluble flux residues from contaminating the PCB during the

manufacturing process. Contaminants such as these can result in unexpected leakage currents and consequent

temperature-measurement errors.

8.3.8 Inductor-DCR-Based Overcurrent Protection

The LM27403 exploits the filter inductor DCR to detect overcurrent events. This technique enables lossless and

continuous monitoring of the output current using an RC sense network in parallel with the inductor. DCR current

sensing allows the system designer to use inductors specified with low tolerance DCRs to improve the current

limit setpoint accuracy. A dc current limit setpoint accuracy within the range of 10% to 15% is easily achieved

using inductors with low DCR tolerances.

8.3.9 Current Sensing: CS+ and CS–

As mentioned, the LM27403 implements an inductor DCR lossless current sense scheme designed to provide

both accurate overload (current limit) and short-circuit protection. Figure 30 shows the popular inductor DCR

current sense method. Figure 31 shows an implementation with current shunt resistor, RISNS.

Components RSand CSin Figure 30 create a low-pass filter across the inductor to enable differential sensing of

the inductor DCR voltage drop. When RSCSis equal to L/Rdcr, the voltage developed across the sense capacitor,

CS, is a replica of the inductor DCR's voltage waveform. Choose the capacitance of CSgreater than 0.1 µF to

maintain low impedance of the sense network, thus reducing the susceptibility of noise pickup from the switch

node.

Product Folder Links: LM27403

24 23

GND

CS±CS+ VIN

VOUT

GND

LM27403

RSCS

RISET

RCS

CCS

Rdcr

9 10

D±

D+

ICS(T)

VIN +

Comparator

dcr OCP

ISET CS

R I 2

§ ·



¨ ¸

VIN

RSCS

Rdcr VOUT

GND

To Load

VIN

VOUT

GND

LRISNS

To Load

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Figure 30. Current Sensing Using Inductor DCR Figure 31. Current Sensing Using Shunt Resistor

The current limit circuit arrangement is portrayed in Figure 32. The current limit setpoint is set by a single

external resistor, RISET, connected from the CS– pin to the output voltage terminal. The current sourced from

CS– in combination with this series resistance sets the reference voltage to the current limit comparator, as

governed by Equation 8.

where

• ICS is the CS– pin current, 9.9 µA typically at 25°C

• IOCP is the dc overcurrent protection setpoint, and

•ΔiLis the peak-to-peak inductor ripple current. (8)

Inductor DCR temperature compensation is automatically provided using the remote-diode sensed temperature.

The temperature coefficient (TC) of the inductor winding resistance is typically 3720 ppm/°C. The current-limit

setpoint is maintained essentially constant over temperature by the slope of CS– pin current over temperature.

An increase in sensed DCR voltage associated with an increase of inductor winding temperature is matched by a

concomitant increase in current limit comparator reference voltage. The inductor temperature is measured by

placing an external diode-connected 2N3904 discrete NPN transistor, designated QTin Figure 32, in close

proximity to the inductor (see the Temperature Sensing: D+ and D– section for more details).

Figure 32. Current-Limit Setpoint Defined by Current Source ICS and Resistor RISET

Product Folder Links: LM27403

SS REF

SS SS

C V

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Note that the inductor DCR is shown schematically as a discrete element in Figure 30 and Figure 32. The

current-sense comparator inputs operate at common mode up to the input rail voltage. The comparator

incorporates a very low input-referred offset to reduce the SNR of the voltage detected across the inductor DCR.

The CS– pin current is specified down to a headroom compliance voltage of less than 0.8 V (that is, VVIN – VCS–)

and over the full operating temperature range (see the Electrical Characteristics Table and Figure 13). The

current source is powered from the input to allow the current limit circuit to work in high duty cycle applications.

With power inductors selected to provide lowest possible DCR to minimize power losses, the typical DCR ranges

from 0.4 mΩto 4 mΩ. Then, given a load current of 25 A, the voltage presented across the CS+ and CS– pins

ranges between 10 mV and 100 mV. Note that this small differential signal is superimposed on a large common-

mode signal that is the dc output voltage, which makes the current sense signal challenging to process. To aid in

rejection of high frequency common-mode noise, a series resistor, RCS, of same resistance as RISET, is added to

the CS+ signal path as shown in Figure 32. A small capacitor, CCS, added across CS+ and CS– provides

differential filtering.

A current sense (or current shunt) resistor in series with the inductor can also be implemented at lower output

current levels to provide accurate overcurrent protection, see Figure 31. Burdened by the unavoidable efficiency

penalty and/or additional cost implications, this configuration is not usually implemented in high-current

applications (except where OCP setpoint accuracy and stability over the operating temperature range are critical

specifications). However, if a shunt resistor is used, temperature compensation is not required. In this case, short

the D+ to D– pins to disable this function. The current sourced from CS– in this case becomes 5 µA (typical) and

is independent of temperature.

In the PCB layout, component pads are recommended to install a small capacitor, designated Cdin Figure 32,

between the D+ and D– pins as close to the LM27403 as possible. This capacitor should not exceed 1 nF for

2N3904-type devices. Locate an additional capacitor, typically 100 pF, at the BJT, when operating in noisy

environments (for example, where leakage flux from the airgap of a ferrite inductor may couple into the adjacent

circuit board traces).

8.3.10 Current Limit Handling

The LM27403 implements a hiccup mode to allow the device to cool down during overcurrent events. If five

overcurrent events are detected during any 32 clock cycle interval, the LM27403 shuts down and stops switching

for a period of 5 ms. During this time, negative inductor current is not allowed, and the output cannot swing

negative. After 5 ms, the LM27403 starts up in the normal startup routine at an output voltage ramp rate

determined by the internal soft-start function or the external soft-start capacitor (if one is used). With each

detected current limit event, the high-side MOSFET is turned off and the low-side MOSFET is turned on.

8.3.11 Soft-Start: SS/TRACK

After the UVLO/EN pin exceeds the rising threshold of 1.15 V, the LM27403 begins charging the output to the dc

level dictated by the feedback resistor network. The LM27403 features an adjustable soft-start (set by a capacitor

from the SS/TRACK pin to GND) that determines the charging time of the output. A 3-µA current source charges

this soft-start capacitor. Soft-start limits inrush current as a result of high output capacitance and avoids an

overcurrent condition. Stress on the input supply rail is also reduced. The soft-start time, tSS, for the output

voltage to ramp to its nominal level is set by Equation 9:

where

• CSS is the soft-start capacitance

• VREF is the 0.6-V reference, and

• ISS is the 3-µA current sourced from the SS/TRACK pin. (9)

If a soft-start capacitor is not used, then the LM27403 defaults to a minimum internal soft-start time of 1.28 ms

and provides a resolution of 128 steps. Thus, the internal soft-start dictates the fastest startup time for the circuit.

When the SS/TRACK voltage exceeds 91% of the reference voltage, the Power Good flag transitions high.

Conversely, the Power Good flag goes low when the SS/TRACK voltage goes below 87% of the reference.

Product Folder Links: LM27403

LM27403

1SS/TRACK

RTRACK1

RTRACK2

41.2 k

10 k

VOUTSLAVE1 = 1.8 V

RFB1

RFB2

20 k

10 k

0.6 V

0.65 V 3

LM27403

1SS/TRACK

RTRACK1

RTRACK2

20 k

RFB1

RFB2

20 k

0.6 V1.5 V

VOUTSLAVE2 = 1.2 V

VOUTMASTER = 3.3 V

Slave Regulator #1

Ratiometric Tracking Slave Regulator #2

Coincident Tracking

VOUT

SS/TRACK

PGOOD

91% VOUT 87% VOUT

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

8.3.11.1 Tracking

The SS/TRACK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This

tracking is achieved by simply dividing down the master's output voltage with a simple resistor network.

Coincident, ratiometric, and offset tracking modes are possible.

If an external voltage source is connected to the SS/TRACK pin, the external soft-start capability of the LM27403

is effectively disabled (the internal soft-start is still enabled). The regulated output voltage level is reached when

the SS/TRACK pin reaches the 0.6-V reference voltage level. It is the responsibility of the system designer to

determine if an external soft-start capacitor is required to keep the device from entering current limit during a

startup event. Likewise, the system designer must also be aware of how fast the input supply ramps if the

tracking feature is enabled.

Figure 33 shows a triangular voltage signal directly driving SS/TRACK and the corresponding output voltage

tracking response. Nominal output voltage here is 1.2 V, with channel scales chosen such that the waveforms

overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 91% (rising) and 87% (falling)

of the nominal output voltage setpoint.

Figure 33. Typical Output Voltage Tracking Waveforms and PGOOD Flag

Two practical tracking configurations, ratiometric and coincident, are shown in Figure 34. The most common

application is coincident tracking, used in core vs. I/O voltage tracking in DSP and FPGA implementations.

Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the

slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the slave's output voltage to a

fraction of the master's output voltage during startup.

Figure 34. Tracking Implementation With Master, Ratiometric Slave and Coincident Slave Rails

Product Folder Links: LM27403

lower COMP clamp

valley of PWM ramp

SS/TRACK

UVLO/EN

COMP

VOUT

EN to SS delay

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

For coincident tracking, connect the slave regulator's SS/TRACK input to a resistor divider from the master's

output voltage that is the same as the divider used on the slave's FB pin. In other words, simply select RTRACK1 =

RFB1 and RTRACK2 = RFB2 as shown in Figure 34. As the master voltage rises, the slave voltage rises identically.

Eventually, the slave voltage reaches its regulation voltage, at which point the internal reference takes over the

regulation while the SS/TRACK input continues to increase, thus removing itself from changing the output

voltage.

In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRACK voltage being too

close to the 0.6-V reference voltage, the final value of the slave's SS/TRACK voltage should be at least 20 mV

above FB.

8.3.12 Monotonic Startup

The LM27403 has monotonic startup capability with no dips or flat spots in the output voltage waveform during

startup (including prebiased startup) and fault recovery. During the soft-start interval, FB follows SS/TRACK, and

the output voltage linearly increases to the nominal output setpoint. Figure 35 illustrates the output voltage

behavior during a monotonic startup to a nominal level of 1.2V. The UVLO/EN pin is driven high by a TTL logic

signal. As mentioned previously, the startup time is determined by the use of an external soft-start capacitor at

the SS/TRACK pin charged by an internally generated 3-µA constant current source. If a soft-start capacitor is

not used, the device automatically enables the internal 7-bit (128 step) digital soft-start. The PGOOD flag

transitions high when FB reaches its 91% threshold. As described previously, there is a calibration interval based

on four cycles on the D+ pin (that is, 512 clock cycles) that creates a delay from UVLO/EN crossing its precision

threshold to SS/TRACK being released.

Figure 35. Typical Monotonic Output Voltage Startup Waveforms, 1.2-V Output

8.3.13 Prebias Startup

In certain applications, the output voltage may have an initial voltage prebias before the LM27403 is powered on

or enabled. The LM27403 is able to startup into a prebiased load while maintaining a monotonic output voltage

startup characteristic.

The LM27403 does not allow switching until the SS/TRACK pin voltage has reached the feedback (FB) voltage

level. Once this level is reached, the controller begins to regulate and switch synchronously, allowing a certain

amount of negative current during PWM switching operation. Thereafter, the feedback voltage follows the soft-

start voltage up to 0.6 V. This is illustrated in Figure 36 where nominal output voltage is 1.2 V and the output

voltage waveform represents twice the FB level. The output is not pulled low during a prebiased startup

condition. Note that if the output is prebiased to a higher voltage than the nominal level (as set by the feedback

resistor divider), the LM27403 does not pull the output low, hence eliminating current flow through parasitic paths

in the system.

Product Folder Links: LM27403

VOUT

SS/TRACK COMP

UVLO/EN

lower COMP clamp

valley of PWM ramp

EN to SS delay

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

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Figure 36. Typical Startup Waveforms With 0.6-V Prebiased Output, 1.2-V Nominal Output

The LM27403 automatically pulls down the SS/TRACK pin to GND before the onset of switching and during a

restart from a fault condition. When SS/TRACK is initially released, subsequent to the temperature sense

calibration delay, the COMP voltage is released to the lower COMP clamp level and no switching occurs. Both

the LG and HG pins are held low while the SS/TRACK voltage stays below the FB voltage level. This action

ensures that a prebiased load is not pulled down by a negative dc output current component. When the

SS/TRACK pin voltage crosses above either FB or VREF, the COMP voltage slews up to the valley of the PWM

ramp and switching begins.

8.3.14 Voltage-Mode Control

The LM27403 incorporates a voltage-mode control loop implementation with input voltage feedforward to

eliminate the input voltage dependence of the PWM modulator gain. This configuration allows the controller to

maintain stability throughout the entire input voltage operating range and provides for optimal response to input

voltage transient disturbances. The constant gain provided by the controller greatly simplifies feedback loop

design because loop characteristics remain constant as the input voltage changes, unlike a buck converter

without voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage

amplitude to maintain constant modulator gain. The input voltage feedforward gain, kFF, is 1/9, equivalent to the

ramp amplitude divided by the input voltage, VRAMP/VIN. See the Control Loop Compensation section for more

detail.

8.3.15 Output Voltage Remote Sense: RS

High-current switching power supplies typically use output voltage remote sensing to achieve the greatest

accuracy at the point of load. There are usually some finite bus structure resistances between the power supply

and load, denoted by lumped elements RBUS+ and RBUS– in Figure 37, that cause unwanted voltage drops or load

regulation errors, particularly at high output currents.

Product Folder Links: LM27403

VIN

VOUT+

GND

Adaptive

Gate

Driver &

Logic

LOAD

3 4

FB COMP

213

GND RS

RFB1

RFB2

CC1

CC2

RC1

RSENSE±

RSENSE+

RBUS+

RBUS±

SENSE+

SENSE±

Error

Amplifier PWM

Comparator

Bandgap

Reference

REF

CRS

CC3 RC2

LM27403

VOUT-

DC/DC Regulator

LM27403

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SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Figure 37. LM27403 Output Remote Sense and Voltage Control Loop

Remote ground sensing is implemented in the LM27403 by bringing another amplifier input, designated RS,

outside of the device package to act as a kelvin ground sense. This circuit is created by replacing the standard

error amplifier used in the PWM loop with a new amplifier that has two pairs of differential inputs. One of the

differential input pairs is used to sense the internal reference voltage relative to the IC ground potential. The

other differential input is used to remotely sense the feedback (FB) voltage relative to RS connected to the

negative load terminal (at the output point of load). The output of the new error amplifier is the difference

between the two pairs of inputs multiplied by some gain factor, and in all other respects works the same as the

classic op-amp type error amplifier.

For accurate remote sensing of the output at the load, make sure to tie upper feedback resistor RFB1 directly to

the load at the point where output regulation is required. However, in order to minimize injected noise into the

high-impedance FB node, connect the RC lead network, RC2 and CC3, typically found across RFB1 in voltage-

mode control loop compensation networks, to the local VOUT connection, as shown in Figure 37. Similarly,

connect the negative sense line locally at the negative load terminal and route both sense lines as a differential

pair to minimize pickup and injected noise. Sense resistors, RSENSE+ and RSENSE–, typically 10 Ωeach, are used

to maintain regulation when the remote sense lines are not connected or as a fail-safe measure if the lines

become disconnected. In particularly noisy environments, capacitor CRS shown in Figure 37 (typically 0.1 µF) is

supplemented by a series resistor (for example, 10 Ω). If remote sense is not required, RS is simply shorted to

GND.

The configuration in Figure 37 avoids the use of a separate unity-gain differential amplifier, a solution commonly

used to perform remote sensing. The offset and gain error of this differential amplifier configuration compound

any inaccuracy associated with the reference and error amplifier input offset voltage. The accuracy of the

feedback system is not compromised when using the method shown in Figure 37. The LM27403 specified

feedback accuracy of ±1% is preserved over the full operating temperature range.

8.3.16 Power Good: PGOOD

To implement an open-drain power-good function for sequencing and fault detection, use the PGOOD pin of the

LM27403. The PGOOD open-drain MOSFET is pulled low during current limit, UVLO, output undervoltage and

overvoltage, or if the output is not regulated.

More specifically, this function can be triggered by multiple events, including the output voltage either exceeding

the overvoltage threshold (117% VREF) or decreasing below the undervoltage threshold (91% VREF), heavy

overcurrent, soft-start voltage (both internal and external) below 91% VREF, UVLO, thermal shutdown, enable

delay, or disabled state.

Product Folder Links: LM27403

LM27403

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To prevent momentary glitches to the PGOOD pin, a 20-µs deglitch filter is built into the LM27403 to prevent

multiple triggerings of the flag. Note that the primary objective of PGOOD is to signal to the system that the soft-

start period has expired and the output voltage is in regulation for loads within the rated limit. This can be used

for sequencing downstream regulators, an example of which is shown schematically in Figure 48.

During soft-start operation, the PGOOD flag is effectively a logic AND of two signals:

1. The internal soft-start counter (signals the internal soft-start-done flag when the count reaches 128).

2. The UVT comparator output. Note that the UVT comparator monitors SS/TRACK voltage until the first PWM

pulse, and then monitors the FB voltage.

The reason for multiplexing the UVT comparator is to support prebias loads and tracking. The PGOOD voltage

waveform is shown in Figure 33 with a 100-kΩpullup resistor to VDD. As described previously, VDD disappears

when UVLO/EN is pulled lower than an effective diode drop (~0.7 V). This does not represent a system-level

issue because PGOOD is already pulled low in that scenario.

8.3.17 Gate Drivers: LG and HG

The LM27403 gate driver impedances are low enough to perform effectively in high output current applications

where large die-size or paralleled MOSFETs with correspondingly large gate charge, QG, are used. Measured at

VVDD = 4.5 V, the LM27403's low-side driver has a low impedance pull-down path of 0.9 Ωto minimize the effect

of dv/dt induced turn-on, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side driver

has 1.5-Ωand 1.0-Ωpull-up and pull-down impedances, respectively, for faster switching transition times, lower

switching loss, and greater efficiency.

Furthermore, there is a proprietary adaptive deadtime control on both switching edges to prevent shoot-through

and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery related

losses. The LM27403 is fully compatible with discrete and Power Block NexFET™ MOSFETs from TI.

8.3.18 Sink and Source Capability

Even though an LM27403-based DC/DC regulator is capable of sinking and sourcing current (as it operates in

CCM), the inductor DCR-based overcurrent protection operates only with positive currents. Negative currents are

detected through the low-side MOSFET only when the device is in an overvoltage condition (refer to Zero Cross

and Negative Current Limit sections). Note that prebias startup still operates normally (refer to Prebias Startup

section).

8.4 Device Functional Modes

8.4.1 Fault Conditions

Overcurrent, overtemperature, output undervoltage and overvoltage protection features are included in the

LM27403.

8.4.1.1 Thermal Shutdown

The LM27403 includes an internal junction temperature monitor. If the temperature exceeds 150°C (typ), thermal

shutdown occurs. When entering thermal shutdown, the device:

1. turns off the low-side and high-side MOSFETs;

2. flushes the external soft-start capacitor;

3. initiates a soft-start sequence when the die temperature decreases by the OTP hysteresis, 20°C (typ).

This is a nonlatching protection, and, as such, the device will cycle into and out of thermal shutdown if the fault

persists.

8.4.1.2 Current Limit and Short Circuit Operation (Positive Overcurrent)

When detecting a current-limit (CL) event, one of the following actions occur:

1. Light CL: When a current limit event is detected, the high-side on-pulse is immediately terminated (HG off,

LG on) and the system continues regulating on the next system clock event;

2. Heavy CL: If five current limit events occur in any 32 clock cycles, the pulse is terminated (HG off, LG off)

and hiccup mode is entered.

Product Folder Links: LM27403

LM27403

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SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Device Functional Modes (continued)

The following actions occur in hiccup mode:

1. HG off, LG off;

2. Re-enable soft-start clock to count 5-ms timeout for hiccup delay;

3. At the end of the hiccup delay, re-enter the startup sequence, including the internal enable delay.

Every time a current limit event is detected, the current limit event counter is incremented on the next clock edge.

If the current limit event counter reaches its threshold of five, then the hiccup mode is entered.

8.4.1.3 Negative Current Limit

Negative current limit detection is in effect only after an overvoltage (OV) condition is met. The OV flag is

deglitched by 10 µs. By the time OV is signaled, the loop has most likely moved into a low- or zero-percent duty

cycle that poses the threat of excessive negative current. Thus, the negative current limit is in effect as soon as

the OV condition is detected rather than waiting for the deglitched version. If the negative current limit is

exceeded, the low-side MOSFET gate (LG pin) is pulled low and the LM27403 enters Negative Current Limit

hiccup mode for 5 ms.

Negative Current Limit hiccup mode (subsequent to OVP) is different from Current Limit hiccup mode in that

zero-cross current detection is active in the latter and the LG output is high. However, as with Current Limit

hiccup mode, the system attempts to restart after the 5-ms timeout, as described in the Current Limit Handling

section. The LM27403 detects a negative current limit by monitoring the switch-node (SW) voltage while the low-

side MOSFET is on. If the switch-node voltage (that is, the low-side MOSFET drain-source voltage) rises 100 mV

above ground during the low-side MOSFET conduction interval, the comparator trips, signaling that the negative

current limit threshold has been reached. The low-side MOSFET is turned off, thus protecting it from excess

current.

The negative current comparator is valid only when the LG is high. Blanking time lasts 20 ns to 50 ns after LG

has been asserted. Blanking recurs as soon as PWM goes high.

8.4.1.4 Undervoltage Threshold (UVT)

The FB pin is also monitored for an output voltage excursion below the nominal level. However, if the UVT

comparator is tripped, no action occurs on the normal switching cycles. The UVT signal is used solely as a valid

condition for the Power Good flag to transition low. When the FB voltage exceeds 91% of the reference voltage,

the Power Good flag transitions high. Conversely, the Power Good flag transitions low when the FB voltage is

less than 87% of the reference.

8.4.1.5 Overvoltage Threshold (OVT)

When the FB voltage exceeds 116.5% of the reference voltage, the Power Good flag transitions low after a 10-µs

deglitch. The control loop attempts to bring the output voltage back to the nominal setpoint. Conversely, when the

FB voltage goes below 113% of the reference, the Power Good flag is allowed to transition high. Negative

current-limit detection is activated when the regulator is in an OV condition. See the Negative Current Limit

section for more details.

Product Folder Links: LM27403

OUT 2 2

sw O ESR L

C8F V (R I )

'  '

OUT IN OUT

IN L sw

V V V

LV I F

§ ·



¨ ¸

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Design and Implementation

To expedite the process of designing of a LM27403-based regulator for a given application, please use the

LM27403 Quick-start Design Tool available as a free download. As well as numerous LM27403 reference

designs populated in TI Designs™ reference design library, five designs are provided in the Typical Applications

section of this datasheet. The LM27403 is also WEBENCH®Designer enabled.

9.1.2 Power Train Components

Comprehensive knowledge and understanding of the power train components are key to successfully completing

a buck regulator design. The LM27403 Design Tool and WEBENCH are available to assist the designer with

selection of these components for a given application.

9.1.2.1 Filter Inductor

For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 20% and 40%

of the maximum dc output current. Choose the inductance using Equation 10:

(10)

Check the inductor datasheet to ensure that the inductor's saturation current is well above the peak inductor

current of a particular design. Ferrite designs have very low core loss and are preferred at high switching

frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core

loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core

materials exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation current

is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to

mention reduced efficiency and compromised reliability. Note that an inductor's saturation current generally

deceases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding

inductor saturation.

9.1.2.2 Output Capacitors

Ordinarily, the regulator’s output capacitor energy store combined with the control loop response are prescribed

to maintain the integrity of the output voltage within both the static and dynamic (transient) tolerance

specifications. The usual boundaries restricting the output capacitor in power management applications are

driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics –

equivalent series resistance (ESR) and equivalent series inductance (ESL) – take increasing precedence in

shaping the regulator’s load transient response as the output current ramp amplitude and slew rate increase.

So, the output capacitor, COUT, exists to filter the inductor ripple current and provide a reservoir of charge for step

load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage

ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively

compact footprint for transient loading events.

Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVO, choose an output

capacitance that is larger than

(11)

Product Folder Links: LM27403

OUT 2 2

OUT overshoot OUT

I L

C(V V ) V

 ' 

load current, io(t)

Io1

Io2

'Io

tramp

Io2

Io1

'Io

inductor current, iL

load current, io(t)

'QC

o o

ramp

di I

dt t

IN OUT

LV V

dt L



OUT

dt L



LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Application Information (continued)

Figure 38 conceptually illustrates the relevant current waveforms during both load step-up and step-down

transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to

match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of

charge in the output capacitor, which must be replenished as rapidly as possible during and after the load-on

transient. Similarly, during and after a load-off transient, the slew rate limiting of the inductor current adds to the

surplus of charge in the output capacitor that needs to be depleted as quickly as possible.

Figure 38. Load Transient Response Representation Showing COUT Charge Surplus Or Deficit.

In a typical regulator application of 12-V input to low output voltage (say 1.2 V), it should be recognized that the

load-off transient represents worst-case. In that case, the steady-state duty cycle is approximately 10% and the

large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –VOUT/L. Compared

to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of

charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess

charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level

following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb

the excess charge and rein in the voltage overshoot.

To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as

ΔVovershoot with step reduction in output current given by ΔIo), the output capacitance should be larger than

(12)

The ESR of a capacitor is provided in the manufacturer’s datasheet either explicitly as a specification or implicitly

in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have

significant ESR, 5 mΩand above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some ESR and

ESL as well. Ceramic output capacitors, on the other hand, are such that the impedances related to the ESR and

ESL are small at the switching frequency, and the capacitive impedance dominates. However, depending on

package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with

applied voltage and operating temperature.

Ignoring the ESR term in Equation 11 gives a quick estimation of the minimum ceramic capacitance necessary to

meet the output ripple specification. One to four 100-µF, 6.3-V, X5R capacitors in 1206 or 1210 footprint is a

common choice. Use Equation 12 to quantify if additional capacitance is necessary to meet the load-off transient

overshoot specification.

Product Folder Links: LM27403

 

IN sw IN ESR o

D 1 D I

CF V DR I



t' 

IN o ESR

sw IN

I D(1 D)

V DI R

F C



' 

CIN,rms o I

I D I (1 D) 12

§ ·

 

¨ ¸

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Application Information (continued)

A composite implementation of ceramic and electrolytic capacitors highlights the rationale of paralleling

capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor

is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range

of interest. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low

ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk

capacitance provides low-frequency energy storage to cope with load-transient demands.

9.1.2.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage while switching-frequency ac current to the buck

power stage. It is generally recommended to use X5R or X7R dielectric ceramic capacitors, thus providing low

impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in

the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and

the source of the low-side MOSFET.

The input capacitors' RMS current is given by Equation 13.

(13)

The highest requirement for input capacitor RMS current rating occurs at D = 0.5, at which point the RMS current

rating should be greater than half the output current.

Ideally, the dc component of input current is provided by the input voltage source and the ac component by the

input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude Io−IIN

during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave

current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component

of ac ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak

ripple voltage amplitude is given by Equation 14.

(14)

The input capacitance required for a particular load current, based on an input voltage ripple specification of

ΔVIN, is given by Equation 15.

(15)

Low ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized

input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with

high-Q ceramics. One bulk capacitor of sufficiently high current rating and one or two 10-μF 25-V X7R ceramic

decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current rating and

operating temperature.

9.1.2.4 Power MOSFETs

The choice of MOSFET has significant impact on DC-DC regulator performance. A MOSFET with low on-state

resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times

and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate charge, QG, and

vice versa. As a result, the product RDS(on)*QGis commonly specified as a MOSFET figure-of-merit. Low thermal

resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting MOSFET selection in an LM27403 application are as follows:

• RDS(on) at VGS = 4.5 V;

• Drain-source voltage rating, BVDSS, typically 25 V or 30 V;

• Gate charge parameters at VGS = 4.5 V;

• Body diode reverse recovery charge, QRR;

• Gate threshold voltage, VGS(th), derived from the plateau in the QGvs. VGS curve in the MOSFET's datasheet.

VGS(th) should be in the range 2 V to 3 V such that the MOSFET is adequately enhanced when on and margin

Product Folder Links: LM27403

low side

RR IN sw RR

P V F Q 

body diode L L

cond F sw o dt1 o dt2

I I

P V F I t I t

2 2

ª º

' '

§ · § ·

  

« »

¨ ¸ ¨ ¸

¬ ¼

high side high side

Gate DD sw G

P V F Q

 

low side low side

Gate DD sw G

P V F Q

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high side L L

sw IN sw o R o F

I I

P V F I t I t

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high side high side

cond o DS(on)

P D I R

 

§ ·



¨ ¸

low side low side

cond o DS(on)

P D' I R

 

§ ·



¨ ¸

LM27403

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SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Application Information (continued)

against Cdv/dt shoot-through exists when off.

The MOSFET-related power losses are summarized by the equations presented in Table 2. While the influence

of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances,

are not discussed. Consult the LM27403 Quick-start Design Tool to assist with power loss calculations.

Table 2. Buck Regulator MOSFET Power Losses

Power Loss Mode High-Side MOSFET Low-Side MOSFET

Conduction (1)

(2)

Switching Negligible

Gate Drive(3)

Body Diode Conduction N/A

Body Diode Reverse Recovery

(1) MOSFET RDS(on) has a positive temperature coefficient of approximately 4000 ppm/°C. The MOSFET junction temperature, TJ, and its

rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance.

(2) D' = 1–D is the duty cycle complement.

(3) Gate drive loss is not dissipated in the MOSFET but rather in the LM27403's integrated drivers.

The high-side (control) MOSFET carries the inductor current during the PWM on time (or D interval) and typically

incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances

conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of

the losses due to conduction, switching and typically two-thirds of the net loss attributed to body diode reverse

recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D

interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just

commutates from the channel to the body diode or vice versa during the deadtime. The LM27403, with its

adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses

scale directly with switching frequency.

In high input voltage and low output voltage applications, the low-side MOSFET carries the current for a large

portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET

for low RDS(on). In cases where the conduction loss is too high or the target RDS(on) is lower than available in a

single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET

is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss

attributed to body diode reverse recovery.

The LM27403 is well matched to TI's comprehensive portfolio of 25-V and 30-V NexFET™ family of power

MOSFETs. In fact, the LM27403 is ideally suited to driving the Power Block NexFET™ modules with integrated

high-side and low-side MOSFETs. Excellent efficiency is obtained by virtue of reduced parasitics and exemplary

thermal performance of the Power Block MOSFET implementation. See the Typical Applications section for more

details.

9.1.3 Control Loop Compensation

The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue

dashed rings in the schematic embedded in Table 3.

Product Folder Links: LM27403

LDAMP

z2 FB2 C2 C3

(R R )C



p2 C1 C1 C2 C1 C2

1 1

R (C C ) R C

oo o

ESR L

o o ESR DAMP

1 1

L C

1 R R

L C 1 R R

§ ·



¨ ¸



ESR ESR o

R C

p1 C2 C3

R C

z1 C1 C1

R C

COMP

VIN

GND

Adaptive

Gate

Driver

RFB2

RC2

CC3

CC2

RFB1

RC1

CC1

VREF

PWM

Comparator

PWM Ramp

&p1

&z1

RESR

&p2

&z2

&ESR

Modulator

Compensator

Power Stage

VRAMP

Error

Amp

RDAMP

Qlow-side

Qhigh-side

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

The compensation network typically employed with voltage-mode control is a type-III circuit with three poles and

two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation

strategy then is to use two compensator zeros to counteract the LC double pole, one compensator pole located

to nullify the output capacitor ESR zero, with the remaining compensator pole located at one-half switching

frequency to attenuate high frequency noise. Finally, a resistor divider network to FB determines the desired

output voltage. Note that the lower feedback resistor, RFB2, has no impact on the control loop from an ac

standpoint since the FB node is the input to an error amplifier and is effectively at ac ground. Hence, the control

loop is designed irrespective of output voltage level. The proviso here is the necessary output capacitance

derating with bias voltage and temperature.

Table 3. Regulator Poles and Zeros

Power Stage Poles Power Stage Zeros Compensator Poles Compensator Zeros

(1)

(2)

(1) RESR represents the ESR of output capacitor Co.

(2) RDAMP = D*RDS(on)high-side + (1–D)*RDS(on)low-side + Rdcr, shown as a lumped element in the schematic, represents the effective series

damping resistance.

The small-signal open-loop response of a buck regulator is the product of modulator, power train and

compensator transfer functions. The power stage transfer function can be represented as a complex pole pair

associated with the output LC filter and a zero related to the output capacitor's ESR. The dc (and low frequency)

gain of the modulator and power stage is VIN/VRAMP. Representing the gain from COMP to the average voltage at

the input of the LC filter, this is held essentially constant by the LM27403's PWM line feedforward feature at 9

V/V or 19 dB.

Complete expressions for small-signal frequency analysis are presented in Table 4. The transfer functions are

denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by

its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio

susceptibility.

Product Folder Links: LM27403

C1 C3 IN

vRAMP

R C V

T (s) s V

-40

-20

-180

-135

-90

-45

110 100 1000

Frequency (kHz)

Loop

Gain

(dB)

Loop

Phase

(°)

Complex

LC Double

Pole

Compensator

Poles

Output

Capacitor

ESR Zero

Crossover

Frequency, fc

Compensator

Zeros

Loop

Phase

Loop

Gain

Mcomp RAMP

d(s) 1

FÖ

v (s) V

comp z2

c mid

p1 p2

1 1

v (s) s

G (s) K

v (s) s s

1 1

Z Z

§ ·

 

¨ ¸

§ ·§ ·

 

¨ ¸¨ ¸

vd IN 2

v (s) 0

i (s) 0 2

v (s)

G (s) V

d(s) s s



 

ESR

o o o

comp o

v c vd M

o comp

v (s) Ö

v (s) d(s)

T (s) G (s)G (s)F

Ö Ö

v (s) v (s)

d(s)

 

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Table 4. Buck Regulator Small-Signal Analysis

PARAMETER EXPRESSION

Open-loop transfer function

Duty-cycle-to-output transfer function

Compensator transfer function(1)

Modulator transfer function

(1) Kmid = RC1/RFB1 is the compensator's mid-band gain. By expressing one of the compensator zeros in inverted zero format, the mid-band

gain is denoted explicitly.

An illustration of the open-loop response gain and phase is given in Figure 39. The poles and zeros of the

system are marked with x and o symbols, respectively, and a + symbol indicates the crossover frequency. When

plotted on a log (dB) scale, the open-loop gain is effectively the sum of the individual gain components from the

modulator, power stage and compensator – this is clear from Figure 40. The open-loop response of the system is

measured experimentally by breaking the loop, injecting a variable-frequency oscillator signal and recording the

ensuing frequency response using a network analyzer setup.

Figure 39. Typical Buck Regulator Loop Gain and Phase With Voltage-Mode Control

If the pole located at ωp1 cancels the zero located at ωESR and the pole at ωp2 is located well above crossover,

the expression for the loop gain, Tv(s) in Table 4, can be manipulated to yield the simplified expression given in

Equation 16.

(16)

Product Folder Links: LM27403

C2 p1 C3

C3 z2 FB1

C2 p2 C1

C1 mid FB1

R K R

 

FB1

FB2 o REF

RV V 1



C1 z1 C1

-40

-20

110 100 1000

Frequency (kHz)

Gain

(dB)

Loop Gain

Filter Gain

Modulator

Gain Compensator

Gain

c mid o

RAMP

2 f K V

Z S Z

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Essentially, a multi-order system is reduced to a single order approximation by judicious choice of compensator

components. A simple solution for the crossover frequency, denoted as fcin Figure 39, with type-III voltage-mode

control is derived as in Equation 17.

(17)

Figure 40. Buck Regulator Constituent Gain Components

The loop crossover frequency is usually selected between one-tenth to one-fifth of switching frequency. Inserting

an appropriate crossover frequency into Equation 17 gives a target for the compensator's mid-band gain, Kmid.

Given an initial value for RFB1, RFB2 is then selected based on the desired output voltage. Values for RC1, RC2,

CC1, CC2 and CC3 are calculated from the design-oriented expressions listed in Table 5, with the premise that the

compensator poles and zeros are set as follows: ωz1 = 0.5ωo,ωz2 =ωo,ωp1 =ωESR,ωp2 =ωsw/2.

Table 5. Compensation Component Selection

RESISTORS CAPACITORS

Referring to the bode plot in Figure 39, the phase margin, indicated as φM, is the difference between the loop

phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase

boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole (hence why

CC1 is scaled by a factor of 2 above). This helps to mitigate the phase dip associated with the LC filter,

particularly at light loads when the Q-factor is higher and the phase dip becomes especially prominent. The

ramification of low phase in the frequency domain is an under-damped transient response in the time domain.

The power supply designer now has all the tools at his/her disposal to optimally position the loop crossover

frequency while maintaining adequate phase margin over the power supply's required line, load and temperature

operating ranges.

Product Folder Links: LM27403

7 8 9 10 11 12

24 23

CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

VIN

VOUT+

GND

LM27403SQ

VOUT+

VIN

D+

D±

VDD

COUT

CIN

CBOOT

RSCS

RISET

RCS

CCS

CVIN RVIN

RUV1

RUV2

RFADJ

RFB2

RC1

RC2

ROTP

CSS

CC3

CC1

CVDD

2N3904

COTP

DBOOT

CC2

82.5 k

2.2 

1 F

4.7 F

10 k

68.1 k

2.55 k

4 x

47 F

1 H

1.1 m

470 pF

56 pF

820 pF

47 nF 0.22 F

47.5 k

3.32 k

4.22 k

3 x

22 F

3.3 nF20 k

SYNC

221 

0.1 F

40V

0.2A

0.1 F

300 kHz

RFB1

20 k

RPGOOD

20 k

VOUT-

SHUTDOWN PG

CBULK

330 F

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

9.2 Typical Applications

9.2.1 Design 1 - High-Efficiency Synchronous Buck Regulator for Telecom Power

Figure 41. Application Circuit 1 with VIN = 6.5 V to 20 V (VIN(nom) = 12 V), VOUT = 0.6 V to 5.3 V, IOUT(max) =

25 A, FSW = 300 kHz (Using External Synchronization Signal)

9.2.1.1 Design Requirements

The schematic diagram of a 25-A regulator is given in Figure 41. In this example, the target full-load efficiencies

are 91% and 97% at 1.2-V and 5.3-V output voltages, respectively, based on a nominal input voltage of 12 V that

ranges from 6.5 V to 20 V. Output voltage is adjusted simply by changing RFB2. The switching frequency is set by

means of a synchronization signal at 300 kHz, and free-running switching frequency (in the event that the

synchronization signal is removed) is set to 250 kHz by resistor RFADJ. In terms of control loop performance, the

target loop crossover frequency is 45 kHz with a phase margin in excess of 50°. The output voltage soft-start

time is 8 ms.

9.2.1.2 Detailed Design Procedure

The design procedure for an LM27403-based converter for a given application is streamlined by using the

LM27403 Quick-Start Design Tool available as a free download, or by availing of TI's WEBENCH® Designer

online software. Such tools are complemented by the availability of two LM27403 evaluation module (EVM)

designs as well as numerous LM27403 reference designs populated in TI Designs™ reference design library.

The current limit setpoint in this design is set at 28.5 A, based on resistor RISET and the inductor DCR (1.1 mΩ

typ at 25°C). Of course, the current limit setpoint should always be selected such that the operating current level

does not exceed the saturation current specification of the chosen inductor. The component values for the DCR

sense network (RSand CSin Figure 41) are chosen based on making the RSCSproduct approximately equal to

L/Rdcr, as recommended in the Current Sensing: CS+ and CS– section.

The selected buck converter powertrain components are cited in Table 6, and many of the components are

available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching

power loss, as discussed in detail in the Power MOSFETs section.

Product Folder Links: LM27403

PGOOD

VIN

VOUT

IOUT

VOUT

IOUT

100

Efficiency (%)

Output Current (A)

C001

VOUT = 5.3V

VOUT = 1.2V

Fsw = 250 kHz

VIN = 12V

VOUT = 1.8V

VOUT = 3.3V

100

Efficiency (%)

Output Current (A)

C001

VIN = 20V

VIN = 3.3V

Fsw = 250 kHz

VOUT = 1.2V

VIN = 5V

VIN = 12V

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Typical Applications (continued)

Table 6. List of Materials for Design 1

REFERENCE QTY SPECIFICATION MANUFACTURER PART NUMBER

DESIGNATOR

Kemet C1210C226M3RACTU

CIN 3 22 µF, 25 V, X7R, 1210 ceramic Taiyo Yuden TMK325B7226MM-TR

Murata GRM32ER71E226KE15L

Taiyo Yuden LMK325B7476MM-TR

COUT 4 47 µF, 10 V, X7R, 1210 ceramic Murata GRM32ER71A476KE15L

CBULK 1 330 µF, 6.3 V, 9 mΩ, D3L POSCAP Sanyo 6TPF330M9L

L11 1.0 µH, 30 A, 1.1 mΩ±10%, ferrite Delta HMP1360-1R0-63

Infineon BSC032NE2LS

Q11 25 V, high-side MOSFET Texas Instruments CSD16322Q5

Infineon BSC010NE2LS

Q21 25 V, low-side MOSFET Texas Instruments CSD16415Q5

9.2.1.3 Application Curves

Figure 42. Efficiency vs. Output Current at VIN = 12 V Figure 43. Efficiency vs. Output Current at VOUT = 1.2 V

Figure 44. Load Transient Response at VOUT = 1.2 V, IOUT Figure 45. Startup Characteristic with VIN stepped from 0 V

0A to 10A at 2A/µs to 12 V, VOUT = 1.2 V, 70-mΩLoad

Product Folder Links: LM27403

7 8 9 10 11 12

24 23

CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

LM27403SQ

D+

D±

COUT

RSCS

RISET

RCS

CCS

CVIN RVIN

RUV1 RUV2

RFADJ

RFB2

RC1

RC2

ROTP

CC3

CC1

CVDD

2N3904

COTP

DBOOT

CC2

84.5 k2.2 

1 F

4.7 F

10 k

15 k

10 k

3 x

100 F

300 nH

0.29 m

100 pF

47 pF

330 pF

0.1 F

26.4 k

3.32 k

2.32 k

3 x

10 F

1 nF10 k

221 

0.1 F

40V

0.2A

0.1 F

RFB1

20 k

VDD

CBOOT

CSD87350Q5D

GND

VIN

TGR BG

CIN

VIN

VOUT

GND

VIN

VOUT RTRK1

RTRK2

VTRACK

20 k

10 k

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

9.2.2 Design 2 - Powering FPGAs Using Flexible 30A Regulator With Small Footprint

Figure 46. Application Circuit 2 With VIN = 4.5 V to 15 V (VIN(nom) = 12 V), VOUT = 1.8 V, IOUT(max) = 30 A, FSW

= 600 kHz

9.2.2.1 Design Requirements

The schematic diagram of a 600-kHz, 30-A regulator is given in Figure 46. The powertrain components are listed

in Table 7.

Table 7. List of Materials for Design 2

REFERENCE QTY SPECIFICATION MANUFACTURER PART NUMBER

DESIGNATOR

Taiyo Yuden TMK212BBJ106KG-T

CIN 3 10 µF, 25 V, X5R, 0805 ceramic Murata GRM21BR61E106KA73L

TDK C2012X5R1E106M

Taiyo Yuden JMK316BJ107ML-T

Murarta GRM31CR60J107ME39L

COUT 1 100 µF, 6.3 V, X5R, 1206 ceramic TDK C3216X5R0J107M

Kemet C1206C107M9PACTU

35 A, 0.29 mΩ±8% Coiltronics FP1107R1-R30-R

300 nH, ferrite 34 A, 0.29 mΩ±7% Cyntec PCDC1107-R30EMO

L11270 nH, ferrite 37 A, 0.24 mΩ±5% Coilcraft SLC1175-271MEC

250 nH, ferrite 44 A, 0.37 mΩ±7% Wurth 744308025

Q11 30 V Power Block Q5D MOSFET Module, 5 mm x 6 mm Texas Instruments CSD87350Q5D

9.2.2.2 Detailed Design Procedure

A high power density, high efficiency solution is feasible by using TI NexFET™ Power Block module

CSD87350Q5D (dual asymmetric MOSFETs in a SON 5-mm x 6-mm package) together with and low-DCR ferrite

inductor and all-ceramic capacitor design. The design occupies 20 mm x 15 mm on a single-sided PCB. Knowing

the cumulative resistance of the inductor DCR and Power Block MOSFET SW clip (approximately 1 mΩat 25°C),

resistor RISET positions the current limit setpoint at 28A. The output voltage is adjusted by choosing the

resistance of RFB2 appropriately. Resistors RTRK1 and RTRK2 connected to the SS/TRACK pin define a

coincidental tracking startup sequence from a master power supply, VTRACK.

Product Folder Links: LM27403

100

0 5 10 15 20 25 30

Efficiency (%)

Output Current (A)

C008

VIN = 12V

VOUT = 3.3V

VOUT = 1.8V

VOUT = 1.2V

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Additional input and/or output capacitance can be added if needed, but adjust the compensation if COUT changes.

The TGR pin of the Power Block MOSFET serves as a kelvin connection to the source of the high-side MOSFET

and represents the return path for the high-side gate drive. Along with bootstrap capacitor, CBOOT, TGR is

connected to the LM27403's SW pin.

9.2.2.3 Application Curves

Figure 47. Efficiency vs. Output Current at VIN = 12 V

Product Folder Links: LM27403

7 8 9 10 11 12

24 23

CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

VOUT

GND

LM27403SQ

VOUT

VIN

D+

D±

CBULK

RSCS

RISET

RCS

CCS

CVIN RVIN

RFADJ

RFB2

RC1

RC2

ROTP

CSS

CC3

CC1

CVDD

2N3904

COTP

DBOOT

CC2

84.5 k2.2 

1 F

4.7 F

23.7 k

8.06 k270 F

0.42 H

1.55 m

220 pF

120 pF

1.5 nF

33 nF 0.1 F

3.48 k

3.01 k

22 F

4.7 nF5.49 k

1 k

0.1 F

40V

0.2A

0.1 F

RFB1

6.81 k

VIN

VDD

CBOOT

CSD87330Q3D

GND

VIN

TGR BG

CIN

LM10011SD

GND

IDAC_OUT

VDD

EN VIDA

VIDC

VIDB

VIDS

SET

MODE RSET

182 k

TMS320C667x

VCNTL[3]

VCNTL[0]

VCNTL[1]

VCNTL[2] KeyStone¥

Multicore

DSP

CVDD U3

0 A ± 59.2 A

0.9 V ± 1.1 V

core voltage

6.4mV step

resolution

DVDD18

RPU1:4

5 x 10 F

CBYPASS

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

9.2.3 Design 3 - Powering Multicore DSPs

Figure 48. Application Circuit 3 with VIN =3Vto20V,VOUT = 0.9 V to 1.1 V, IOUT(max) = 15 A, FSW = 450 kHz

The schematic diagram of a 450-kHz, 12-V nominal input, 15-A regulator powering a KeyStone™ DSP is given in

Figure 48. The important components are listed in Table 8. The regulator output current requirements are

dependent upon the baseline and activity power consumptions of the DSP in a real-use case. While baseline

power is highly dependent on voltage, temperature and DSP frequency, activity power relates to dynamic core

utilization, DDR3 memory access, peripherals, and so on. To this end, the IDAC_OUT pin of the LM10011

connects to the LM27403 FB pin to allow continuous optimization of the core voltage. The SmartReflex-enabled

DSP provides 6-bit information using the VCNTL open-drain IOs(1) to command the output voltage setpoint with

6.4-mV step resolution. This design uses a TI NexFET™ Power Block module CSD87330Q3D (dual asymmetric

MOSFETs in SON 3.3-mm x 3.3-mm package) together with low-DCR, metal-powder inductor and composite

ceramic–polymer electrolytic output capacitor implementation.

Table 8. List of Materials for Design 3

REFERENCE QTY SPECIFICATION MANUFACTURER PART NUMBER

DESIGNATOR

CIN 1 22 µF, 25 V, X5R, 1210 ceramic Taiyo Yuden TMK325BJ226MM-T

CBYPASS 5 10 µF, 4 V, X5R, 0402 ceramic Taiyo Yuden AMK105BJ106MV-F

CBULK 1 270 µF, 2 V, 6 mΩ, 3.2 Arms, 3.5 mm x 2.8 mm, POSCAP Panasonic 2TPSF270M6E

L11 0.42 µH, 22 A, 1.55 mΩ±7%, molded, 6.9 mm x 6.6 mm Cyntec PIME064T-R42MS1R557

Q11 30 V Power Block Q3D MOSFET Module, 3.3 mm x 3.3 mm Texas Instruments CSD87330Q3D

QT1 2N3904 type NPN transistor, 40 V, 0.2 A, SOT-523 Diodes, Inc. MMBT3904T

U21 6- or 4-bit VID Programmable Current DAC, WSON-10 Texas Instruments LM10011SD

U31 KeyStone™ DSP Texas Instruments TMS320C667x

(1) See TI Application Report entitled Hardware Design Guide for Keystone I Devices SPRAB12 for further detail.

Product Folder Links: LM27403

7 8 9 10 11 12

24 23

CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

VIN

GND

LM27403SQ

VOUT1

VIN VIN

D+

D±

VDD

CBYP

CIN

CBOOT

RSCS

RISET

RCS

CCS

CVIN RVIN

RUV1 RUV2

RFADJ

RFB2

RC1

RC2

ROTP

CSS

CC3

CC1

CVDD

2N3904

COTP

DBOOT

CC2

82.5 k2.2 

1 F

4.7 F

2 k

52.3 k

1.05 k

22 F

4.7 H

7 m

100 pF

47 pF

1.2 nF

47 nF 0.22 F

20 k

10.5 k

3.65 k

3 x

22 F

4.7 nF22.1 k

2 k

0.1 F

40V 0.2A

0.1 F

RFB1

20 k

U1RBOOT

10 

CBULK

180 F

VOUT1 = 12V

GND

OUT

OUT(FB)

SET

GND

IN(CP)

GND(CP)

LP38798SD-ADJ

CCP

10 nF

73.5 k

10 k

CV2

1 F

CLDO_IN

1 F

VOUT1 VOUT2 = 10V

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

9.2.4 Design 4 - Regulated 12-V Rail with LDO Low-Noise Auxiliary Output for RF Power

Figure 49. Application Circuit 4 with VIN =13Vto20V(VIN(nom) = 18 V), VOUT1 = 12 V, IOUT1(max) = 10 A, FSW

= 280 kHz, VOUT2 = 10 V, IOUT2(max) = 0.8 A

The schematic diagram of a 280-kHz, 12-V output, 10-A buck regulator for RF power applications is given in

Figure 49(1). A 10-Ωresistor in series with CBOOT is used to slow the turn-on transition of the high-side MOSFET,

reducing the spike amplitude and ringing of the SW node waveform and minimizing the possibility of Cdv/dt-

induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ωand 1 nF)

close to the SW node and GND(2). An auxiliary 10-V, 800-mA rail to power noise-sensitive circuits is available

using the LP38798 ultra-low noise LDO as a post-regulator. The internal pullup of the LP38798's EN pin

facilitates direct connection to the LM27403's PGOOD for sequential startup control.

Table 9. List of Materials for Design 4

REFERENCE QTY SPECIFICATION MANUFACTURER PART NUMBER

DESIGNATOR

CIN 3 22 µF, 25 V, X5R, 1210 ceramic Taiyo Yuden TMK325BJ226MM-T

CBYP 1 22 µF, 16 V, X7R, 1210 ceramic Taiyo Yuden EMK325B7226MM-T

CBULK 1 180 µF, 16 V, 22 mΩ, 3.3 Arms, C6, OSCON Panasonic 16SVPF180M

L11 4.7 µH, 15 A, 7 mΩ, flat wire high current Wurth 7443551470

Q11 30 V, high-side MOSFET Texas Instruments CSD17309Q3

Q21 30 V, low-side MOSFET Infineon BSC011NE3LS

Ultra-Low Noise, High PSRR LDO for RF/Analog

U21 Texas Instruments LP38798SD-ADJ

Circuits, 4-mm x 4-mm WSON-12

(1) These design examples are provided to showcase the LM27403 in numerous applications. Depending on the impedance of the input

bus, an electrolytic capacitor may be required at the input to ensure stability.

(2) Kam, K. W. and others, "EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis," IEEE International

Symposium on Electromagnetic Compatibility, 2008.

Product Folder Links: LM27403

7 8 9 10 11 12

24 23

CBOOT

VDD

GND

SS/TRACK

COMP

FADJ

SYNC

UVLO

/EN

OTP

D+

D±

PGOOD

VIN

CS±

CS+

LM27403SQ

D+

D±

COUT

RSCS

RISET

RCS

CCS

CVIN RVIN

RFADJ

RFB2

RC1

RC2

ROTP

CC3

CSS

2N3904

COTP

DBOOT

CC2

84.5 k2.2 

10 F

61.9 k

15 k

4 x

100 F

300 nH

0.29 m

220 pF

390 pF

1 nF

0.1 F

3.4 k

2.32 k

33 nF

3.4 k

301 

0.22 F

40V

0.2A

0.1 F

RFB1

10 k

VDD

CBOOT

CSD87353Q5D

GND

VIN

TGR BG

CIN

VIN

VOUT

GND

VIN

VOUT

CC1

4.7 nF

x 2

CDLY

4.7 nF

3 x

100 F

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

9.2.5 Design 5 - High Power Density Implementation From 3.3-V or 5-V Supply Rail

Figure 50. Application Circuit 5 With VIN = 3.3 V to 5.5 V, VOUT =1V,IOUT(max) = 25 A, FSW = 250 kHz

The schematic diagram of a 250-kHz, 25-A regulator is given in Figure 50. A high power density, ultra-high

efficiency solution is possible using two paralleled TI CSD87353Q5D NexFET™ Power Block modules (dual

MOSFETs in a SON 5-mm x 6-mm package) and low-DCR ferrite inductor. The design occupies 25 mm x 15 mm

on a two-sided PCB. Knowing the cumulative resistance of the inductor DCR and Power Block MOSFET SW clip

(approximately 0.8 mΩat 25°C), resistor RISET positions the current limit setpoint at 30A. VDD is tied to VIN to

maximize the gate drive voltage for the MOSFETs. Capacitor CDLY defines a 3-ms startup delay based on the

current sourced from the UVLO/EN pin.

The powertrain components are listed in Table 10, and the filter components are available from multiple vendors.

The TGR pin of the Power Block MOSFET serves as a kelvin connection to the source of the high-side MOSFET

and represents the return path for the high-side gate drive. Along with bootstrap capacitor, CBOOT, TGR is

connected to the LM27403's SW pin.

Table 10. List of Materials for Design 5

REFERENCE QTY SPECIFICATION MANUFACTURER PART NUMBER

DESIGNATOR

Kemet C1210C107M9PACTU

CIN 3 100 µF, 6.3 V, X5R, 1210 ceramic TDK C3225X5R0J107M

Murata GRM32ER60J107ME20K

Taiyo Yuden JMK316BJ107ML-T

Murarta GRM31CR60J107ME39L

COUT 4 100 µF, 6.3 V, X5R, 1206 ceramic TDK C3216X5R0J107M

Kemet C1206C107M9PACTU

300 nH, ferrite 35 A, 0.29 mΩ±8% Coiltronics FP1107R1-R30-R

L11330 nH, ferrite 46 A, 0.32 mΩ±7% Wurth Electronik 744301033

Q12 30 V Power Block Q5D MOSFET Module, 5 mm x 6 mm Texas Instruments CSD87353Q5D

Product Folder Links: LM27403

CBOOT

VDD

GND

VIN

VOUT

GND

LM27403

VDD

Low-side

gate

driver

High-side

gate

driver

CVDD

CBOOT

CIN

COUT

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

10 Power Supply Recommendations

The LM27403 PWM controller is designed to operate from an input voltage supply range between 3 V and 20 V.

If the input supply is located more than a few inches from the LM27403-based converter, additional bulk

capacitance may be required in addition to ceramic bypass capacitance. Given the negative incremental input

impedance of a buck converter, a bulk electrolytic component provides damping to reduce effects of input

parasitic inductance resonating with high-Q ceramics.

11 Layout

11.1 Layout Guidelines

Proper PCB design and layout is important in a high current, fast switching circuit (with high current and voltage

slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must be

considered before designing a PCB layout using the LM27403. The main switching loop of the power stage is

denoted by #1 in Figure 51. The topological architecture of a buck converter means that particularly high di/dt

current will flow in loop #1, and it becomes mandatory to reduce the parasitic inductance of this loop by

minimizing its effective loop area. For loop #2 however, the di/dt through inductor L1and capacitor COUT is

naturally limited by the inductor. Keeping the area of loop #2 small is not nearly as important as that of loop #1.

Also important are the gate drive loops of the low-side and high-side MOSFETs, denoted by #3 and #4,

respectively, in Figure 51.

Figure 51. DC-DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops

11.1.1 Power Stage Layout

1. Input capacitor(s), output capacitor(s) and MOSFETs are the constituent components in the power stage of a

buck regulator and are typically placed on the top side of the PCB (solder side). Leveraging any system-level

airflow, the benefits of convective heat transfer are thus maximized. In a two-sided PCB layout, small-signal

components are typically placed on the bottom side (component side). At least one inner plane should be

inserted, connected to ground, in order to shield and isolate the small-signal traces from noisy power traces

and lines.

2. The DC-DC converter has several high-current loops. Minimize the area of these loops in order to suppress

generated switching noise and parasitic loop inductance and optimize switching performance.

– Loop #1: The most important loop to minimize the area of is the path from the input capacitor(s) through

the high- and low-side MOSFETs, and back to the capacitor(s) through the ground connection. Connect

the input capacitor(s) negative terminal close to the source of the low-side MOSFET (at ground).

Similarly, connect the input capacitor(s) positive terminal close to the drain of the high-side MOSFET (at

Product Folder Links: LM27403

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Layout Guidelines (continued)

VIN). Refer to loop #1 of Figure 51.

– Loop #2. The second important loop is the path from the low-side MOSFET through inductor and output

capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side

MOSFET and negative terminal of the output capacitor(s) at ground as close as possible. Refer to loop

#2 of Figure 51.

3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the

drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, should be short and

wide. However, the SW connection is a source of injected EMI and thus should not be too large.

4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including

pad geometry and solder paste stencil design.

5. The SW pin connects to the switch node of the power conversion stage, and it acts as the return path for the

high-side gate driver. The parasitic inductance inherent to loop #1 in Figure 51 and the output capacitance

(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (>100 MHz) ringing on

the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input

voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the

SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to

GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network

components in the printed circuit board layout. If testing reveals that the ringing amplitude at the SW pin is

excessive, then include snubber components.

11.1.2 Gate Drive Layout

The LM27403 high- and low-side gate drivers incorporate short propagation delays, adaptive deadtime control

and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to

facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause unacceptable

ringing if the trace lengths and impedances are not well controlled.

Minimization of stray/parasitic loop inductance is key to optimizing gate drive switching performance, whether it

be series gate inductance that resonates with MOSFET gate capacitance or common source inductance

(common to gate and power loops) that provides a negative feedback component opposing the gate drive

command, thereby increasing MOSFET switching times. The following loops are important:

• Loop #3: high-side MOSFET, Q1. During the high-side MOSFET turn on, high current flows from the boot

capacitor through the gate driver and high-side MOSFET, and back to negative terminal of the boot capacitor

through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from gate of the

high-side MOSFET through the gate driver and SW, and back to source of the high-side MOSFET through

the SW trace. Refer to loop #3 of Figure 51.

• Loop #4: low-side MOSFET, Q2. During the low-side MOSFET turn on, high current flows from VDD

decoupling capacitor through the gate driver and low-side MOSFET, and back to negative terminal of the

capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from gate of the

low-side MOSFET through the gate driver and GND, and back to source of the low-side MOSFET through

ground. Refer to loop #4 of Figure 51.

The following circuit layout guidelines are strongly recommended when designing with high-speed MOSFET gate

drive circuits.

1. Connections from gate driver outputs, HG and LG, to the respective gate of the high-side or low-side

MOSFET should be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or

wider traces. Use via(s), if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HG

and SW gate traces as a differential pair from the LM27403 to the high-side MOSFET, taking advantage of

flux cancellation.

2. Minimize the current loop path from the VDD and CBOOT pins through their respective capacitors as these

provide the high instantaneous current to charge the MOSFET gate capacitances. Specifically, locate the

bootstrap capacitor, CBOOT, close to the LM27403's CBOOT and SW pins to minimize the area of loop #3

associated with the high-side driver. Similarly, locate the VDD capacitor, CVDD, close to the LM27403's VDD

and GND pins to minimize the area of loop #4 associated with the low-side driver.

3. Placing a 2-Ωto 10-ΩBOOT resistor in series with the BOOT capacitor, as shown in Figure 49, slows down

the high-side MOSFET turn-on transition, serving to reduce the voltage ringing and peak amplitude at the

SW node at the expense of increased MOSFET turn-on power loss.

Product Folder Links: LM27403

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

Layout Guidelines (continued)

11.1.3 Controller Layout

Components related to the analog and feedback signals, current limit setting and temperature sense are

considered in the following:

1. In general, separate power and signal traces, and use a ground plane to provide noise shielding.

2. Place all sensitive analog traces and components such as COMP, FB, RS, FADJ, OTP, D+ and SS/TRACK

away from high-voltage switching nodes such as SW, HG, LG or CBOOT avoid coupling. Use internal

layer(s) as ground plane(s). Pay particular attention to shielding the feedback (FB) trace from power traces

and components.

3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or

the bulk capacitor at the converter side. Connect RS to the ground return point at the load device or the

general ground plane/layer. These connections can be used for the purpose of remote sensing across the

downstream load; however, care must be taken to minimize the routing trace to prevent noise injection into

the sense lines. The remote sense lines (SENSE+ and SENSE- in Figure 37) are typically routed as a

differential pair, either side-by-side on the same PCB layer or overlapping each other on adjacent layers.

4. Connect the OCP setting resistor from CS+ pin to VOUT and make the connections as close as possible to

the LM27403. The trace from the CS+ pin to the resistor should avoid coupling to a high-voltage switching

node. Similar precautions apply if a resistor is tied to the CS– pin (as shown in Figure 32).

5. Minimize the current loop from the VDD and VIN pins through their respective decoupling capacitors to the

GND pin. In other words, locate these capacitors as close as possible to the LM27403.

6. The layout of the temperature sense circuit is particularly important. Locate the thermal diode (2N3904-type

BJT) adjacent the inductor on the same side of the PCB if possible. Close thermal coupling to the inductor is

imperative to match the inductor winding's temperature coefficient.

(a) Keep D+ and D– traces close together to minimize pickup. 10-mil trace width with 10-mil spacing is

adequate. Keep D+ and D– traces short and surround with ground guard copper in especially noisy

environments.

(b) Route traces away from inductor, particularly with ferrite cores that have wide airgap and large

fringing/leakage flux fields. Run a separate trace from the 2N3904 emitter back to LM27403 D– pin. Then

connect D– to GND at the LM27403's DAP. Do not use a ground plane that carries high currents to make

a return connection.

11.1.4 Thermal Design and Layout

The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO

regulator is greatly affected by:

• average gate drive current requirements of the power MOSFETs;

• switching frequency;

• operating input voltage (affecting LDO voltage drop and hence its power dissipation);

• thermal characteristics of the package and operating environment.

In order for a PWM controller to be useful over a particular temperature range, the package must allow for the

efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM27403

controller is available in a small 4-mm x 4-mm WQFN-24 (RSW) PowerPAD™ package to cover a range of

application requirements. The thermal metrics of this package are summarized in the Thermal Information

section of this datasheet. For detailed information regarding the thermal information table, please refer to IC

Package Thermal Metrics,SPRA953, application report.

The WQFN-24 package offers a means of removing heat from the semiconductor die through the exposed

thermal pad at the base of the package. While the exposed pad of the LM27403's package is not directly

connected to any leads of the package, it is thermally connected to the substrate of the device (ground). This

allows a significant improvement in heat-sinking, and it becomes imperative that the PCB is designed with

thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem. The LM27403's

exposed pad is soldered to the ground-connected copper land on the PCB directly underneath the device

package, reducing the thermal resistance to a very low value. Wide traces of the copper tying in the LM27403's

no-connect pins (pins 19–23) and connection to this thermal land helps to dissipate heat.

Product Folder Links: LM27403

LM27403

www.ti.com

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

Layout Guidelines (continued)

Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground

plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the

PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow

but it also represents a thermally conductive path away from the heat generating devices.

The thermal characteristics of the MOSFETs also are significant. The high-side MOSFET's drain pad is normally

connected to a VIN plane for heat-sinking. The low-side MOSFET's drain pad is tied to the SW plane, but the SW

plane area is purposely kept relatively small to mitigate EMI concerns.

11.2 Layout Example

Figure 52 shows an example PCB layout based on the LM27403 25A EVM design. For more details, please see

the LM27403 EVM User's Guide,SNVU233.

Figure 52. LM27403 PCB Layout

Product Folder Links: LM27403

LM27403

SNVS896B –AUGUST 2013–REVISED NOVEMBER 2014

www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

• TI NexFET™ Power Block Module CSD87330Q3D

•LM27403 Design Tool

•PowerLab™

12.1.2 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

•LM27403EVM User's Guide,SNVU233

•LM27403EVM-POL600 User's Guide,SNVU330

•6/4-Bit VID Programmable Current DAC for Point of Load Regulators with Adjustable Start-Up Current,

SNVS822

•High PSRR, Ultra Low Noise, 800 mA Linear Voltage Regulator for RF/Analog Circuits,SNOSCT6

12.3 Trademarks

PowerPAD, and Power Block NexFET are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LM27403

PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM27403SQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L27403

LM27403SQE/NOPB ACTIVE WQFN RTW 24 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L27403

LM27403SQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L27403

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2014

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM27403SQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM27403SQE/NOPB WQFN RTW 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM27403SQX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Mar-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM27403SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LM27403SQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0

LM27403SQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Mar-2018

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

24X 0.3

0.2

24X 0.5

0.3

0.8 MAX

(0.1) TYP

0.05

0.00

20X 0.5

2.5

2X 2.5

2.6 0.1

A4.1

3.9 B

4.1

3.9

WQFN - 0.8 mm max heightRTW0024A

PLASTIC QUAD FLATPACK - NO LEAD

4222815/A 03/2016

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

613

7 12

24 19

(OPTIONAL)

PIN 1 ID 0.1 C A B

0.05 C

EXPOSED

THERMAL PAD

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

24X (0.25)

24X (0.6)

( ) TYP

VIA

0.2

20X (0.5)

(3.8)

(1.05)

( 2.6)

(R )

TYP

0.05

(1.05)

WQFN - 0.8 mm max heightRTW0024A

PLASTIC QUAD FLATPACK - NO LEAD

4222815/A 03/2016

SYMM

712

SYMM

LAND PATTERN EXAMPLE

SCALE:15X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

24X (0.6)

24X (0.25)

20X (0.5)

(3.8)

4X ( 1.15)

(0.675)

TYP

(0.675) TYP

(R ) TYP0.05

WQFN - 0.8 mm max heightRTW0024A

PLASTIC QUAD FLATPACK - NO LEAD

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

712

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consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and

take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will

thoroughly test such applications and the functionality of such TI products as used in such applications.

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,

including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to

assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any

way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource

solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI

products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,

enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically

described in the published documentation for a particular TI Resource.

Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that

include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE

TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY

RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or

endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR

REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO

ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL

PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,

INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF

PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,

DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN

CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949

and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such

products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards

and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must

ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in

life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.

Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life

support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all

medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).

Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications

and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory

requirements in connection with such selection.

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-

compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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