CAT1024YI-30-GT3 - ON Semiconductor

May, 2018 − Rev. 21

1Publication Order Number:

CAT1024/D

CAT1024, CAT1025

Supervisory Circuits with

EEPROM Serial 2k-bit I2C

and Manual Reset

Description

The CAT1024 and CAT1025 are complete memory and supervisory

solutions for microcontroller−based systems. A 2k−bit serial

EEPROM memory and a system power supervisor with brown−out

protection are integrated together in low power CMOS technology.

Memory interface is via a 400 kHz I2C bus.

The CAT1025 provides a precision VCC sense circuit and two open

drain outputs: one (RESET) drives high and the other (RESET) drives

low whenever VCC falls below the reset threshold voltage. The

CAT1025 also has a Write Protect input (WP). Write operations are

disabled if WP is connected to a logic high.

The CAT1024 also provides a precision VCC sense circuit, but has

only a RESET output and does not have a Write Protect input.

All supervisors have a 1.6 second watchdog timer circuit that resets

a system to a known state if software or a hardware glitch halts or

“hangs” the system. For the CAT1024 and CAT1022, the watchdog

timer monitors the SDA signal. The CAT1023 has a separate watchdog

timer interrupt input pin, WDI.

The power supply monitor and reset circuit protect memory and

system controllers during power up/down and against brownout

conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V

systems. If power supply voltages are out of tolerance reset signals

become active, preventing the system microcontroller, ASIC or

peripherals from operating. Reset signals become inactive typically

200 ms after the supply voltage exceeds the reset threshold level. With

both active high and low reset signals, interface to microcontrollers

and other ICs is simple. In addition, the RESET pin or a separate input,

MR, can be used as an input for push−button manual reset capability.

The CAT1024/25 memory features a 16−byte page. In addition,

hardware data protection is provided by a VCC sense circuit that

prevents writes to memory whenever VCC falls below the reset

threshold or until VCC reaches the reset threshold during power up.

Available packages include a surface mount 8−pin SOIC, 8−pin

TSSOP, 8−pin TDFN and 8−pin MSOP packages. The TDFN package

thickness is 0.8 mm maximum. TDFN footprint is 3 x 3 mm.

Features

•Precision Power Supply Voltage Monitor

♦5 V, 3.3 V and 3 V Systems

♦Five Threshold Voltage Options

•Active High or Low Reset

♦Valid Reset Guaranteed at VCC = 1 V

•400 kHz I2C Bus

•2.7 V to 5.5 V Operation

•Low Power CMOS Technology

•16−Byte Page Write Buffer

•Built−in Inadvertent Write Protection

♦WP Pin (CAT1025)

•1,000,000 Program/Erase Cycles

•Manual Reset Input

•100 Year Data Retention

•Industrial and Extended Temperature Ranges

•Green Packages Available with NiPdAu Lead Finished

•These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

ORDERING INFORMATION

www.onsemi.com

SOIC−8

CASE 751BD

TSSOP−8

CASE 948S

MSOP−8

CASE 846AD

TDFN−8

CASE 511AL

For Ordering Information details, see page 13.

CAT1024, CAT1025

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Table 1. THRESHOLD VOLTAGE OPTION

Part Dash

Number

Minimum

Threshold

Maximum

Threshold

−45 4.50 4.75

−42 4.25 4.50

−30 3.00 3.15

−28 2.85 3.00

−25 2.55 2.70

BLOCK DIAGRAM

2kbit

DOUT

ACK

SENSEAMPS

SHIFT REGISTERS

CONTROL

LOGIC

WORDADDRESS

BUFFERS

START/ STOP

LOGIC

EEPROM

VCC

EXTERNAL LOAD

COLUMN

DECODERS

XDEC

DATA IN STORAGE

HIGHVOLTAGE/

TIMING CONTROL

VSS

SDA

RESET Controller

Precision

Vcc Monitor

STATE COUNTERS

SLAVE

ADDRESS

COMPARATORS

RESET* RESET

WP*

*CAT1025 Only

CAT1024, CAT1025

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PIN CONFIGURATION

TSSOP Package (Y)

MSOP Package (Z)

(Bottom View)

TDFN Package: 3 mm x 3 mm

0.8mm maximum height − (ZD4)

SOIC Package (W)

DIP Package (L)

RESET

VSS

VCC

SCL

SDA

CAT1024

RESET

VSS

VCC

SCL

SDA

CAT1025

RESET

VSS

VCC

SCL

SDA

CAT1024

RESET

VSS

VCC

WDI

SCL

SDA

CAT1025

PIN DESCRIPTION

RESET/RESET: RESET OUTPUTs

(RESET CAT1025 Only)

These are open drain pins and RESET can be used as a

manual reset trigger input. By forcing a reset condition on

the pin the device will initiate and maintain a reset condition.

The RESET pin must be connected through a pull−down

resistor, and the RESET pin must be connected through a

pull−up resistor.

SDA: SERIAL DATA ADDRESS

The bidirectional serial data/address pin is used to transfer

all data into and out of the device. The SDA pin is an open

drain output and can be wire−ORed with other open drain or

open collector outputs.

SCL: SERIAL CLOCK

Serial clock input.

MR: MANUAL RESET INPUT

Manual Reset input is a debounced input that can be

connected to an external source for Manual Reset. Pulling

the MR input low will generate a Reset condition. Reset

outputs are active while MR input is low and for the reset

timeout period after MR returns to high. The input has an

internal pull up resistor.

WP (CAT1025 Only): WRITE PROTECT INPUT

When WP input is tied to VSS or left unconnected write

operations to the entire array are allowed. When tied to VCC,

the entire array is protected. This input has an internal pull

down resistor.

Table 2. PIN FUNCTION

Pin Name Function

NC No Connect

RESET Active Low Reset Input/Output

VSS Ground

SDA Serial Data/Address

SCL Clock Input

RESET Active High Reset Output

(CAT1025 Only)

VCC Power Supply

WP Write Protect (CAT1025 Only)

MR Manual Reset Input

Table 3. OPERATING TEMPERATURE RANGE

Industrial −40°C to 85°C

Extended −40°C to 125°C

CAT1024, CAT1025

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Table 4. CAT102X FAMILY OVERVIEW

Device Manual Reset

Input Pin

Watchdog Watchdog

Monitor Pin

Write

Protection

Independent

Auxiliary Voltage

Sense

RESET:

Active High

and LOW

EEPROM

CAT1021 n n SDA n n 2k

CAT1022 n n SDA 2k

CAT1023 n n WDI n2k

CAT1024 n2k

CAT1025 n n n 2k

CAT1026 n n 2k

CAT1027 nWDI n2k

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

SPECIFICATIONS

Table 5. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Temperature Under Bias –55 to +125 °C

Storage Temperature –65 to +150 °C

Voltage on any Pin with Respect to Ground (Note 1) −2.0 to VCC + 2.0 V

VCC with Respect to Ground −2.0 to 7.0 V

Package Power Dissipation Capability (TA = 25°C) 1.0 W

Lead Soldering Temperature (10 s) 300 °C

Output Short Circuit Current (Note 2) 100 mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum

DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.

2. Output shorted for no more than one second. No more than one output shorted at a time.

Table 6. D.C. OPERATING CHARACTERISTICS

VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.

Symbol Parameter Test Conditions Min Typ Max Units

ILI Input Leakage Current VIN = GND to VCC −2 10 mA

ILO Output Leakage Current VIN = GND to VCC −10 10 mA

ICC1 Power Supply Current (Write) fSCL = 400 kHz

VCC = 5.5 V

3 mA

ICC2 Power Supply Current (Read) fSCL = 400 kHz

VCC = 5.5 V

1 mA

ISB Standby Current VCC = 5.5 V

VIN = GND or VCC

40 mA

VIL (Note 3) Input Low Voltage −0.5 0.3 x VCC V

VIH (Note 3) Input High Voltage 0.7 x VCC VCC + 0.5 V

VOL Output Low Voltage

(SDA, RESET)

IOL = 3 mA

VCC = 2.7 V

0.4 V

VOH Output High Voltage

(RESET)

IOH = −0.4 mA

VCC = 2.7 V

VCC − 0.75 V

CAT1024, CAT1025

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Table 6. D.C. OPERATING CHARACTERISTICS

VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.

Symbol UnitsMaxTypMinTest ConditionsParameter

VTH Reset Threshold CAT102x−45

(VCC = 5.0 V)

4.50 4.75 V

CAT102x−42

(VCC = 5.0 V)

4.25 4.50

CAT102x−30

(VCC = 3.3 V)

3.00 3.15

CAT102x−28

(VCC = 3.3 V)

2.85 3.00

CAT102x−25

(VCC = 3.0 V)

2.55 2.70

VRVALID Reset Output Valid VCC Voltage 1.00 V

VRT (Note 4) Reset Threshold Hysteresis 15 mV

3. VIL min and VIH max are reference values only and are not tested.

4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.

Table 7. CAPACITANCE

TA = 25°C, f = 1.0 MHz, VCC = 5 V

Symbol Test Test Conditions Max Units

COUT (Note 5) Output Capacitance VOUT = 0 V 8 pF

CIN (Note 5) Input Capacitance VIN = 0 V 6 pF

Table 8. AC CHARACTERISTICS

VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.

Memory Read & Write Cycle (Note 6)

Symbol Parameter Min Max Units

fSCL Clock Frequency 400 kHz

tSP Input Filter Spike Suppression (SDA, SCL) 100 ns

tLOW Clock Low Period 1.3 ms

tHIGH Clock High Period 0.6 ms

tR (Note 5) SDA and SCL Rise Time 300 ns

tF (Note 5) SDA and SCL Fall Time 300 ns

tHD; STA Start Condition Hold Time 0.6 ms

tSU; STA Start Condition Setup Time (for a Repeated Start) 0.6 ms

tHD; DAT Data Input Hold Time 0 ns

tSU; DAT Data Input Setup Time 100 ns

tSU; STO Stop Condition Setup Time 0.6 ms

tAA SCL Low to Data Out Valid 900 ns

tDH Data Out Hold Time 50 ns

tBUF (Note 5) Time the Bus must be Free Before a New Transmission Can Start 1.3 ms

tWC (Note 7) Write Cycle Time (Byte or Page) 5 ms

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. Test Conditions according to “AC Test Conditions” table.

7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

CAT1024, CAT1025

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Table 9. RESET CIRCUIT AC CHARACTERISTICS

Symbol Parameter Test Conditions Min Typ Max Units

tPURST Power−Up Reset Timeout Note 2 130 200 270 ms

tRDP VTH to RESET output Delay Note 3 5ms

tGLITCH VCC Glitch Reject Pulse Width Notes 4 and 5 30 ns

MR Glitch Manual Reset Glitch Immunity Note 1 100 ns

tMRW MR Pulse Width Note 1 5ms

tMRD MR Input to RESET Output Delay Note 1 1ms

Table 10. POWER−UP TIMING (Notes 5 and 6)

Symbol Parameter Test Conditions Min Typ Max Units

tPUR Power−Up to Read Operation 270 ms

tPUW Power−Up to Write Operation 270 ms

Table 11. AC TEST CONDITIONS

Parameter Test Conditions

Input Pulse Voltages 0.2 x VCC to 0.8 x VCC

Input Rise and Fall Times 10 ns

Input Reference Voltages 0.3 x VCC , 0.7 x VCC

Output Reference Voltages 0.5 x VCC

Output Load Current Source: IOL = 3 mA; CL = 100 pF

Table 12. RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units

NEND (Note 5) Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte

TDR (Note 5) Data Retention MIL−STD−883, Test Method 1008 100 Years

VZAP (Note 5) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 Volts

ILTH (Notes 5 & 7) Latch−Up JEDEC Standard 17 100 mA

1. Test Conditions according to “AC Test Conditions” table.

2. Power−up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

3. Power−Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.

7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to VCC + 1 V.

CAT1024, CAT1025

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DEVICE OPERATON

Reset Controller Description

The CAT1024/25 precision RESET controllers ensure

correct system operation during brownout and power

up/down conditions. They are configured with open drain

RESET outputs.

During power−up, the RESET outputs remain active until

VCC reaches the VTH threshold and will continue driving the

outputs for approximately 200 ms (tPURST) after reaching

VTH. After the tPURST timeout interval, the device will cease

to drive the reset outputs. At this point the reset outputs will

be pulled up or down by their respective pull up/down

resistors.

During power−down, the RESET outputs will be active

when VCC falls below VTH. The RESET output will be valid

so long as VCC is > 1.0 V (VRVALID). The device is designed

to ignore the fast negative going VCC transient pulses

(glitches).

Reset output timing is shown in Figure 1.

Manual Reset Operation

The RESET pin can operate as reset output and manual

reset input. The input is edge triggered; that is, the RESET

input will initiate a reset timeout after detecting a high to low

transition.

When RESET I/O is driven to the active state, the 200 ms

timer will begin to time the reset interval. If external reset is

shorter than 200 ms, Reset outputs will remain active at least

200 ms.

The CAT1024/25 also have a separate manual reset input.

Driving the MR input low by connecting a pushbutton

(normally open) from MR pin to GND will generate a reset

condition. The input has an internal pull up resistor.

Reset remains asserted while MR is low and for the Reset

Timeout period after MR input has gone high.

Glitches shorter than 100 ns on MR input will not generate

a reset pulse. No external debouncing circuits are required.

Manual reset operation using MR input is shown in Figure 2.

Hardware Data Protection

The CAT1024/25 supervisors have been designed to solve

many of the data corruption issues that have long been

associated with serial EEPROMs. Data corruption occurs

when incorrect data is stored in a memory location which is

assumed to hold correct data.

Whenever the device is in a Reset condition, the

embedded EEPROM is disabled for all operations,

including write operations. If the Reset output(s) are active,

in progress communications to the EEPROM are aborted

and no new communications are allowed. In this condition

an internal write cycle to the memory can not be started, but

an in progress internal nonvolatile memory write cycle can

not be aborted. An internal write cycle initiated before the

Reset condition can be successfully finished if there is

enough time (5ms) before VCC reaches the minimum value

of 2 V.

In addition, the CAT1025 includes a Write Protection

Input which when tied to VCC will disable any write

operations to the device.

CAT1024, CAT1025

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Figure 1. RESET Output Timing

GLITCH

VCC PURST

PURST

tRPD

RVALID

VTH

RESET

RESET

RPD

Figure 2. MR Operation and Timing

RESET

tMRD tPURST

tMRW

CAT1024, CAT1025

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EMBEDDED EEPROM OPERATON

The CAT1024 and CAT1025 feature a 2−kbit embedded

serial EEPROM that supports the I2C Bus data transmission

protocol. This Inter−Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter and

any device receiving data to be a receiver. The transfer is

controlled by the Master device which generates the serial

clock and all START and STOP conditions for bus access.

Both the Master device and Slave device can operate as

either transmitter or receiver, but the Master device controls

which mode is activated.

I2C Bus Protocol

The features of the I2C bus protocol are defined as

follows:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition.

Start Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT1024/25 monitors the SDA

and SCL lines and will not respond until this condition is

met.

Stop Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant bits

of the 8−bit slave address are programmable in metal and the

default is 1010.

The last bit of the slave address specifies whether a Read

or Write operation is to be performed. When this bit is set to

1, a Read operation is selected, and when set to 0, a Write

operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1024/25 monitors the bus and

responds with an acknowledge (on the SDA line) when its

address matches the transmitted slave address. The

CAT1024/25 then perform a Read or Write operation

depending on the R/W bit.

Figure 3. Bus Timing

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA tDH

Figure 4. Write Cycle Timing

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK8TH BIT

BYTE n

SCL

SDA

CAT1024, CAT1025

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ACKNOWLEDGE

After a successful data transfer, each receiving device is

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

The CAT1024/25 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

When the CAT1024/25 begins a READ mode it transmits

8 bits of data, releases the SDA line and monitors the line for

an acknowledge. Once it receives this acknowledge, the

CAT1024/25 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information (with

the R/W bit set to zero) to the Slave device. After the Slave

generates an acknowledge, the Master sends a 8−bit address

that is to be written into the address pointers of the device.

After receiving another acknowledge from the Slave, the

Master device transmits the data to be written into the

addressed memory location. The CAT1024/25

acknowledges once more and the Master generates the

STOP condition. At this time, the device begins an internal

programming cycle to non−volatile memory. While the

cycle is in progress, the device will not respond to any

request from the Master device.

Figure 5. Start/Stop Timing

START BIT

STOP BIT

SCL

Figure 6. Acknowledge Timing

ACKNOWLEDGE

RTSTA

SCL FROM

MASTER 8

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 7. Slave Address Bits

Default Configuration 010000R/W

CAT1024, CAT1025

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Page Write

The CAT1024/25 writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The page write

operation is initiated in the same manner as the byte write

operation, however instead of terminating after the initial

byte is transmitted, the Master is allowed to send up to 15

additional bytes. After each byte has been transmitted, the

CAT1024/25 will respond with an acknowledge and

internally increment the lower order address bits by one. The

high order bits remain unchanged.

If the Master transmits more than 16 bytes before sending

the STOP condition, the address counter ‘wraps around,’

and previously transmitted data will be overwritten.

When all 16 bytes are received, and the STOP condition

has been sent by the Master, the internal programming cycle

begins. At this point, all received data is written to the

CAT1024/25 in a single write cycle.

Figure 8. Byte Write Timing

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE

Figure 9. Page Write Timing

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+15

BYTE

ADDRESS (n)

DATA n

DATA n+1

SLAVE

ADDRESS

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is issued

to indicate the end of the host’s write operation, the

CAT1024/25 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the start

condition followed by the slave address for a write

operation. If the device is still busy with the write operation,

no ACK will be returned. If a write operation has completed,

an ACK will be returned and the host can then proceed with

the next read or write operation.

WRITE PROTECTION PIN (WP)

The Write Protection feature (CAT1025 only) allows the

user to protect against inadvertent memory array

programming. If the WP pin is tied to VCC, the entire

memory array is protected and becomes read only. The

CAT1025 will accept both slave and byte addresses, but the

memory location accessed is protected from programming

by the device’s failure to send an acknowledge after the first

byte of data is received.

READ OPERATIONS

The READ operation for the CAT1024/25 is initiated in

the same manner as the write operation with one exception,

the R/W bit is set to one. Three different READ operations

are possible: Immediate/Current Address READ,

Selective/Random READ and Sequential READ.

CAT1024, CAT1025

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Figure 10. Immediate Address Read Timing

SCL

SDA8TH BIT

STOPNO ACKDATA OUT

SLAVE

ADDRESS

DATA N

BUS ACTIVITY:

MASTER

SDA LINE

Immediate/Current Address Read

The CAT1024 and CAT1025 address counter contains the

address of the last byte accessed, incremented by one. In

other words, if the last READ or WRITE access was to

address N, the READ immediately following would access

data from address N + 1. For N = E = 255, the counter will

wrap around to zero and continue to clock out valid data.

After the CAT1024/1025 receives its slave address

information (with the R/W bit set to one), it issues an

acknowledge, then transmits the 8−bit byte requested. The

master device does not send an acknowledge, but will

generate a STOP condition.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte addresses of the location it wishes to read.

After the CAT1024 and CAT1025 acknowledges, the Master

device sends the START condition and the slave address

again, this time with the R/W bit set to one. The CAT1024

and CAT1025 then responds with its acknowledge and sends

the 8−bit byte requested. The master device does not send an

acknowledge but will generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by either

the Immediate Address READ or Selective READ

operations. After the CAT1024 and CAT1025 sends the

initial 8− bit byte requested, the Master will responds with

an acknowledge which tells the device it requires more data.

The CAT1024 and CAT1025 will continue to output an 8−bit

byte for each acknowledge, thus sending the STOP

condition.

The data being transmitted from the CAT1024 and

CAT1025 is sent sequentially with the data from address N

followed by data from address N + 1. The READ operation

address counter increments all of the CAT1024 and

CAT1025 address bits so that the entire memory array can

be read during one operation.

Figure 11. Selective Read Timing

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BYTE

ADDRESS (n)

DATA n

SLAVE

ADDRESS

CAT1024, CAT1025

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Figure 12. Sequential Read Timing

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+xDATA n

DATA n+1

DATA n+2

SLAVE

ADDRESS

ORDERING INFORMATION

Orderable Part Numbers − CAT1024 Series

(See Notes 1 − 5)

Device Reset Threshold Package Shipping†

CAT1024WI−45−GT3 4.50 V − 4.75 V

SOIC

3000 Tape & Reel

CAT1024WI−42−GT3 4.25 V − 4.50 V

CAT1024WI−30−GT3 3.00 V − 3.15 V

CAT1024WI−28−GT3 2.85 V − 3.00 V

CAT1024WI−25−GT3 2.55 V − 2.70 V

CAT1024YI−45−GT3 4.50 V − 4.75 V

TSSOP

CAT1024YI−42−GT3 4.25 V − 4.50 V

CAT1024YI−30−GT3 3.00 V − 3.15 V

CAT1024YI−28−GT3 2.85 V − 3.00 V

CAT1024YI−25−GT3 2.55 V − 2.70 V

CAT1024ZI−45−GT3 4.50 V − 4.75 V

MSOP

CAT1024ZI−42−GT3 4.25 V − 4.50 V

CAT1024ZI−30−GT3 3.00 V − 3.15 V

CAT1024ZI−25−GT3 2.55 V − 2.70 V

CAT1024ZD4I−45T3* 4.50 V − 4.75 V

TDFN

CAT1024ZD4I−42T3* 4.25 V − 4.50 V

CAT1024ZD4I−30T3* 3.00 V − 3.15 V

CAT1024ZD4I−28T3* 2.85 V − 3.00 V

CAT1024ZD4I−25T3* 2.55 V − 2.70 V

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

1. All packages are RoHS−compliant (Lead−free, Halogen−free).

2. The standard lead finish is NiPdAu.

3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.

4. TDFN not available in NiPdAu (–G) version.

5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com

CAT1024, CAT1025

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Orderable Part Numbers − CAT1025 Series

(See Notes 1 − 5)

Device Reset Threshold Package Shipping†

CAT1025WI−45−GT3 4.50 V − 4.75 V

SOIC

3000 Tape & Reel

CAT1025WI−42−GT3 4.25 V − 4.50 V

CAT1025WI−30−GT3 3.00 V − 3.15 V

CAT1025WI−28−GT3 2.85 V − 3.00 V

CAT1025WI−25−GT3 2.55 V − 2.70 V

CAT1025YI−45−GT3 4.50 V − 4.75 V

TSSOP

CAT1025YI−42−GT3 4.25 V − 4.50 V

CAT1025YI−30−GT3 3.00 V − 3.15 V

CAT1025YI−28−GT3 2.85 V − 3.00 V

CAT1025YI−25−GT3 2.55 V − 2.70 V

CAT1025ZI−45−GT3 4.50 V − 4.75 V

MSOP

CAT1025ZI−42−GT3 4.25 V − 4.50 V

CAT1025ZI−30−GT3 3.00 V − 3.15 V

CAT1025ZI−28−GT3 2.85 V − 3.00 V

CAT1025ZI−25−GT3 2.55 V − 2.70 V

CAT1025ZD4I−45T3* 4.50 V − 4.75 V

TDFN

CAT1025ZD4I−42T3* 4.25 V − 4.50 V

CAT1025ZD4I−30T3* 3.00 V − 3.15 V

CAT1025ZD4I−28T3* 2.85 V − 3.00 V

CAT1025ZD4I−25T3* 2.55 V − 2.70 V

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

1. All packages are RoHS−compliant (Lead−free, Halogen−free).

2. The standard lead finish is NiPdAu.

3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.

4. TDFN not available in NiPdAu (–G) version.

5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com

ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol.

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

DATE 19 DEC 2008

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0

Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

REFERENCE:

DESCRIPTION:

98AON34272E

ON SEMICONDUCTOR STANDARD

SOIC 8, 150 MILS

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98AON34272E

PAGE 2 OF 2

ISSUE REVISION DATE

ORELEASED FOR PRODUCTION FROM POD #SOIC8−002−01 TO ON

SEMICONDUCTOR. REQ. BY B. BERGMAN.

19 DEC 2008

December, 2008 − Rev. 01O

Case Outline Number:

751BD

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

TDFN8, 3x3

CASE 511AL−01

ISSUE A

DATE 24 MAR 2009

SIDE VIEW BOTTOM VIEW

TOP VIEW

PIN#1 INDEX AREA

PIN#1 ID

FRONT VIEW

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.23 0.30 0.37

D 2.90 3.00 3.10

D2 2.20 −−− 2.50

E 3.00

E2 1.40 −−− 1.80

2.90

0.65 TYP

3.10

L 0.20 0.30 0.40

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0

Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

REFERENCE:

DESCRIPTION:

98AON34340E

ON SEMICONDUCTOR STANDARD

TDFN8, 3X3

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98AON34340E

PAGE 2 OF 2

ISSUE REVISION DATE

ORELEASED FOR PRODUCTION FROM POD #TDFN8−040−02 TO ON

SEMICONDUCTOR. REQ. BY B. BERGMAN.

19 DEC 2008

ACHANGED DESCRIPTION FROM WDFN TO TDFN. 24 MAR 2009

March, 2009 − Rev. 01A

Case Outline Number:

511AL