TPS731xx www.ti.com .......................................................................................................................................... SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection FEATURES DESCRIPTION * The TPS731xx family of low-dropout (LDO) linear voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR, and even allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current. 1 2 * * * * * * * * * * Stable with No Output Capacitor or Any Value or Type of Capacitor Input Voltage Range of 1.7V to 5.5V Ultralow Dropout Voltage: 30mV Typ Excellent Load Transient Response--with or without Optional Output Capacitor New NMOS Topology Provides Low Reverse Leakage Current Low Noise: 30VRMS Typ (10kHz to 100kHz) 0.5% Initial Accuracy 1% Overall Accuracy over Line, Load, and Temperature Less Than 1A Max IQ in Shutdown Mode Thermal Shutdown and Specified Min/Max Current Limit Protection Available in Multiple Output Voltage Versions - Fixed Outputs of 1.20V to 5.0V - Adjustable Outputs from 1.20V to 5.5V - Custom Outputs Available The TPS731xx uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 1A and ideal for portable applications. The extremely low output noise (30VRMS with 0.1F CNR) is ideal for powering VCOs. These devices are protected by thermal shutdown and foldback current limit. APPLICATIONS * * * * Portable/Battery-Powered Equipment Post-Regulation for Switching Supplies Noise-Sensitive Circuitry such as VCOs Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors space Optional VIN DBV PACKAGE SOT23 (TOP VIEW) Optional IN VOUT OUT TPS731xx EN GND NR ON OFF Optional IN 1 GND 2 EN 3 5 OUT 4 NR/FB Typical Application Circuit for Fixed-Voltage Versions 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2009, Texas Instruments Incorporated TPS731xx SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 .......................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable (3)). YYY is package designator. Z is package quantity. TPS731xx yy yz (1) (2) (3) (2) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet or see the TI website at www.ti.com. Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM programming. Minimum order quantities apply; contact factory for details and availability. For fixed 1.20V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS over operating junction temperature range unless otherwise noted (1) PARAMETER TPS731xx UNIT VIN range -0.3 to 6.0 V VEN range -0.3 to 6.0 V VOUT range -0.3 to 5.5 V VNR, VFB range -0.3 to 6.0 V Peak output current Internally limited Output short-circuit duration Indefinite Continuous total power dissipation See Dissipation Ratings Table Junction temperature range, TJ -55 to +150 Storage temperature range C -65 to +150 C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. POWER DISSIPATION RATINGS (1) BOARD RJC RJA DERATING FACTOR ABOVE TA = 25C TA 25C POWER RATING TA = 70C POWER RATING TA = 85C POWER RATING Low-K (2) DBV 64C/W 255C/W 3.9mW/C 390mW 215mW 155mW High-K (3) DBV 64C/W 180C/W 5.6mW/C 560mW 310mW 225mW (1) (2) (3) 2 PACKAGE See Power Dissipation in the Applications section for more information related to thermal design. The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top of the board. The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board. Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated TPS731xx www.ti.com .......................................................................................................................................... SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5V (1), IOUT = 10mA, VEN = 1.7V, and COUT = 0.1F, unless otherwise noted. Typical values are at TJ = +25C. PARAMETER TEST CONDITIONS VIN Input voltage range (1) VFB Internal reference (TPS73101) VOUT%/VIN Accuracy (1) TYP MAX 1.7 V 1.210 V V 1.198 VFB 5.5 - VDO Nominal TJ = +25C -0.5 +0.5 VIN, IOUT, and T VOUT + 0.5V VIN 5.5V; 10 mA IOUT 150mA -1.0 (2) (3) Line regulation (1) VOUT(nom) + 0.5V VIN 5.5V 1.20 0.5 +1.0 0.01 1mA IOUT 150mA 0.002 10mA IOUT 150mA 0.0005 UNIT 5.5 TJ = +25C Output voltage range (TPS73101) VOUT MIN % %/V VOUT%/IOUT Load regulation VDO Dropout voltage (4) (VIN = VOUT (nom) - 0.1V) IOUT = 150mA ZO(DO) Output impedance in dropout 1.7 V VIN VOUT + VDO ICL Output current limit VOUT = 0.9 x VOUT(nom) ISC Short-circuit current VOUT = 0V 200 IREV Reverse leakage current (5) (-IIN) VEN 0.5V, 0V VIN VOUT 0.1 10 IOUT = 10mA (IQ) 400 550 IOUT = 150mA 550 750 VEN 0.5V, VOUT VIN 5.5, -40C TJ +100C 0.02 1 A 0.1 0.3 A 30 100 mV 500 mA 0.25 150 360 IGND GND pin current ISHDN Shutdown current (IGND) IFB FB pin current (TPS73101) PSRR Power-supply rejection ratio (ripple rejection) f = 100Hz, IOUT = 150 mA 58 f = 10kHz, IOUT = 150 mA 37 VN Output noise voltage BW = 10Hz - 100kHz COUT = 10F, No CNR 27 x VOUT COUT = 10F, CNR = 0.01F 8.5 x VOUT tSTR Startup time VEN(HI) EN pin high (enabled) VEN(LO) EN pin low (shutdown) IEN(HI) EN pin current (enabled) TSD Thermal shutdown temperature TJ Operating junction temperature (1) (2) (3) (4) (5) %/mA VOUT = 3V, RL = 30 COUT = 1F, CNR = 0.01F mA A A dB VRMS s 600 1.7 VIN 0 0.5 V 0.1 A VEN = 5.5V 0.02 Shutdown Temp increasing +160 Reset Temp decreasing +140 -40 V C +125 C Minimum VIN = VOUT + VDO or 1.7V, whichever is greater. TPS73101 is tested at VOUT = 2.5V. Tolerance of external resistors not included in this specification. VDO is not measured for fixed output versions with VOUT(nom) < 1.8V since minimum VIN = 1.7V. Fixed-voltage versions only; refer to the Applications section for more information. Copyright (c) 2003-2009, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS731xx SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 .......................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAMS IN 4MHz Charge Pump EN Thermal Protection Ref Servo 27k Bandgap Error Amp Current Limit OUT 8k GND R1 R1 + R2 = 80k R2 NR Figure 1. Fixed Voltage Version IN Table 1. Standard 1% Resistor Values for Common Output Voltages 4MHz Charge Pump EN Thermal Protection Ref Servo 27k Bandgap Error Amp GND 8k R1 R2 1.2V Short Open 1.5V 23.2k 95.3k 1.8V 28.0k 56.2k 2.5V 39.2k 36.5k 2.8V 44.2k 33.2k 3.0V 46.4k 30.9k 3.3V 52.3k 30.1k NOTE: VOUT = (R1 + R2)/R2 x 1.204; R1R2 19k for best accuracy. OUT Current Limit VO 80k R1 FB R2 Figure 2. Adjustable Voltage Version 4 Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated TPS731xx www.ti.com .......................................................................................................................................... SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 PIN CONFIGURATION DBV PACKAGE SOT23 (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 NR/FB PIN DESCRIPTIONS NAME SOT23 (DBV) PIN NO. DESCRIPTION IN 1 Input supply GND 2 Ground EN 3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to IN if not used. NR 4 Fixed voltage versions only--connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. FB 4 Adjustable voltage version only--this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 Output of the regulator. There are no output capacitor requirements for stability. Copyright (c) 2003-2009, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS731xx SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 .......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS For all voltage versions at TJ= +25C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1F, unless otherwise noted. LOAD REGULATION LINE REGULATION 0.5 0.20 Referred to IOUT = 10mA 0.4 Change in VOUT (%) 0.3 Change in VOUT (%) Referred to VIN = VOUT + 0.5V at IOUT = 10mA 0.15 0.2 0.1 0 -0.1 -0.2 -0.3 0.10 0 -0.05 -40_ C -0.10 -0.15 -0.4 -0.20 -0.5 0 15 30 45 60 75 90 105 120 135 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN - VOUT (V) IOUT (mA) Figure 3. Figure 4. DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE 50 50 TPS73125DBV +125_ C 40 30 +25_ C 20 10 40 VDO (mV) VDO (mV) +25_ C +125_C 0.05 0 30 60 90 120 30 20 10 -40_C 0 TPS73125DBV IOUT = 150mA 0 -50 150 IOUT (mA) -25 0 25 50 75 100 125 Temperature (_ C) Figure 5. Figure 6. OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM 30 18 I OUT = 10mA 16 25 I OUT = 10mA All Voltage Versions Percent of Units (%) Percent of Units (%) 14 20 15 10 12 10 8 6 4 5 2 0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 0 VOUT Error (%) Worst Case dVOUT/dT (ppm/_ C) Figure 7. 6 Submit Documentation Feedback Figure 8. Copyright (c) 2003-2009, Texas Instruments Incorporated TPS731xx www.ti.com .......................................................................................................................................... SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= +25C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1F, unless otherwise noted. GROUND PIN CURRENT vs TEMPERATURE 700 600 600 500 500 IGND (A) IGND (A) GROUND PIN CURRENT vs OUTPUT CURRENT 700 400 300 200 IOUT = 150mA 400 300 VIN = 5.5V VIN = 4V VIN = 2V 200 VIN = 5.5V VIN = 4V VIN = 2V 100 100 0 0 30 60 90 120 0 -50 150 -25 0 I OUT (mA) Figure 9. 50 75 100 125 Figure 10. GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE CURRENT LIMIT vs VOUT (FOLDBACK) 400 1 TPS73133 VENABLE = 0.5V VIN = VO + 0.5V 350 Output Current (mA) IGND (A) 25 Temperature (_ C) 0.1 ICL 300 250 ISC 200 150 100 50 0.01 -50 -25 0 25 50 75 100 0 -0.5 125 0 0.5 Figure 11. 1.5 2.0 2.5 3.0 3.5 Figure 12. CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE 500 500 450 450 400 400 Current Limit (mA) Current Limit (mA) 1.0 Output Voltage (V) Temperature (_C) 350 300 250 200 350 300 250 200 150 1.5 2.0 2.5 3.0 3.5 4.0 VIN (V) Figure 13. Copyright (c) 2003-2009, Texas Instruments Incorporated 4.5 5.0 5.5 150 -50 -25 0 25 50 75 100 125 Temperature (_C) Figure 14. Submit Documentation Feedback 7 TPS731xx SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 .......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= +25C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1F, unless otherwise noted. PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN - VOUT 90 40 IOUT = 100mA COUT = Any Ripple Rejection (dB) 70 40 35 30 IOUT = 1mA COUT = 10mF 60 50 IOUT = 1mA COUT = 1mF IO = 100mA C O = 1m F IOUT = 1mA COUT = Any 30 20 0 VIN = VOUT + 1V 10 100 1k 10k 20 15 Frequency = 10kHz COUT = 10mF VOUT = 2.5V IOUT = 100mA 10 IOUT = 100mA COUT = 10mF IOUT = Any COUT = 0mF 10 25 PSRR (dB) 80 5 0 100k 1M 0 10M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VIN - VOUT (V) Frequency (Hz) Figure 15. Figure 16. NOISE SPECTRAL DENSITY CNR = 0F NOISE SPECTRAL DENSITY CNR = 0.01F 1 1 COUT = 0F 0.1 COUT = 10F eN (V/Hz) eN (V/Hz) C OUT = 1F COUT = 1F 0.1 COUT = 0F COUT = 10F I OUT = 150mA I OUT = 150mA 0.01 0.01 10 100 1k 10k 100k 10 100 Frequency (Hz) 1k 10k 100k Frequency (Hz) Figure 17. Figure 18. RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR 60 140 50 120 VOUT = 5.0V VOUT = 5.0V 100 30 VN (RMS) VN (RMS) 40 VOUT = 3.3V 20 20 CNR = 0.01F 10Hz < Frequency < 100kHz 0.1 0 1 COUT (F) Figure 19. 8 Submit Documentation Feedback 10 VOUT = 3.3V 60 40 VOUT = 1.5V 10 0 80 VOUT = 1.5V COUT = 0F 10Hz < Frequency < 100kHz 1p 10p 100p 1n 10n CNR (F) Figure 20. Copyright (c) 2003-2009, Texas Instruments Incorporated TPS731xx www.ti.com .......................................................................................................................................... SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= +25C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1F, unless otherwise noted. TPS73133 LOAD TRANSIENT RESPONSE VIN = 3.8V TPS73133 LINE TRANSIENT RESPONSE COUT = 0F 40mV/tick IOUT = 150mA VOUT COUT = 0F 50mV/div COUT = 1F 40mV/tick COUT = 10F 40mV/tick VOUT VOUT VOUT COUT = 100F 50mV/div IOUT 25mA/tick 10mA 4.5V 1V/div VIN 10s/div Figure 21. Figure 22. TPS73133 TURN-ON RESPONSE TPS73133 TURN-OFF RESPONSE RL = 1k COUT = 0F = 0.5V/s dt 10s/div RL = 20 COUT = 10F VOUT RL = 20 CO UT = 1F R L = 20 C OUT = 1F 1V/div RL = 1k COUT = 0F RL = 20 COUT = 10F VOUT 2V 2V VEN 1V/div 1V/div 0V 0V 100s/div Figure 23. Figure 24. IENABLE vs TEMPERATURE 10 6 5 4 VEN 100s/div TPS73133 POWER UP / POWER DOWN VIN VOUT IENABLE (nA) 3 Volts dVIN 5.5V 150mA 1V/div VOUT 2 1 1 0.1 0 -1 -2 50ms/div 0.01 -50 -25 0 25 50 75 100 125 Temperature (_C) Figure 25. Copyright (c) 2003-2009, Texas Instruments Incorporated Figure 26. Submit Documentation Feedback 9 TPS731xx SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 .......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= +25C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1F, unless otherwise noted. TPS73101 IFB vs TEMPERATURE 60 160 55 140 50 120 45 100 IFB (nA) VN (rms) TPS73101 RMS NOISE VOLTAGE vs CFB 40 35 30 25 80 60 VOUT = 2.5V COUT = 0F R1 = 39.2k 10Hz < Frequency < 100kHz 20 10p 100p 40 20 1n 10n 0 -50 -25 CFB (F) 0 25 50 75 100 Figure 27. Figure 28. TPS73101 LOAD TRANSIENT, ADJUSTABLE VERSION TPS73101 LINE TRANSIENT, ADJUSTABLE VERSION CFB = 10nF R1 = 39.2k COUT = 0F 50mV/div VOUT COUT = 0F 100mV/div COUT = 10F 100mV/div COUT = 10F 50mV/div 125 Temperature (_C) VOUT = 2.5V CFB = 10nF VOUT VOUT VOUT 4.5V 150mA 3.5V VIN 10mA 25s/div Figure 29. 10 Submit Documentation Feedback IOUT 5s/div Figure 30. Copyright (c) 2003-2009, Texas Instruments Incorporated TPS731xx www.ti.com .......................................................................................................................................... SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 APPLICATION INFORMATION The TPS731xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS731xx ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. Figure 31 shows the basic circuit connections for the fixed voltage models. Figure 32 gives the connections for the adjustable output version (TPS73101). Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN VOUT OUT TPS731xx EN GND NR ON OFF Optional bypass capacitor to reduce output noise. Figure 31. Typical Application Circuit for Fixed-Voltage Versions Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN Optional output capacitor. May improve load transient, noise, or PSRR. EN OFF VOUT OUT TPS73101 GND R1 CFB FB ON R2 VOUT = (R1 + R2) R2 x 1.204 Optional capacitor reduces output noise and improves transient response. Figure 32. Typical Application Circuit for Adjustable-Voltage Version R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values for common output voltages are shown in Figure 2. Copyright (c) 2003-2009, Texas Instruments Incorporated For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19k. This 19k, in addition to the internal 8k resistor, presents the same impedance to the error amp as the 27k bandgap reference output. This impedance helps compensate for leakages into the error amp terminals. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1F to 1F low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS731xx does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50nF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. OUTPUT NOISE A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS731xx and it generates approximately 32VRMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: VOUT (R1 ) R2) V N + 32mVRMS + 32mVRMS R2 VREF (1) Since the value of VREF is 1.2V, this relationship reduces to: mVV V N(mVRMS) + 27 RMS V OUT(V) (2) for the case of no CNR. Submit Documentation Feedback 11 TPS731xx SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 .......................................................................................................................................... www.ti.com An internal 27k resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: mVV V N(mVRMS) + 8.5 RMS V OUT(V) (3) for CNR = 10nF. This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section. The TPS73101 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance. The TPS731xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates ~250V of switching noise at ~4MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin (GND) of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. INTERNAL CURRENT LIMIT The TPS731xx internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5V. See Figure 12 in the Typical Characteristics section. Note from Figure 12 that approximately -0.2V of VOUT results in a current limit of 0mA. Therefore, if OUT is forced below -0.2V before EN goes high, the device may not start up. In applications that work with both a positive and negative voltage supply, the TPS731xx should be enabled first. 12 Submit Documentation Feedback ENABLE PIN AND SHUTDOWN The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5V (max) turns the regulator off and drops the GND pin current to approximately 10nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT (see Figure 23). When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may overshoot upon power-up. Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section. DROPOUT VOLTAGE The TPS731xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS-ON of the NMOS pass element. For large step changes in load current, the TPS731xx requires a larger voltage drop from VIN to VOUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the dc dropout. Values of VIN - VOUT above this line insure normal transient response. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (VIN - VOUT) close to dc dropout levels], the TPS731xx can take a couple of hundred microseconds to return to the specified regulation accuracy. Copyright (c) 2003-2009, Texas Instruments Incorporated TPS731xx www.ti.com .......................................................................................................................................... SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 TRANSIENT RESPONSE The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1F) from the output pin (OUT) to ground will reduce undershoot magnitude but increase its duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response. The TPS731xx does not have active pull-down when the output is over-voltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by: (Fixed voltage version) VOUT dVdt + C OUT 80kW o R LOAD (4) (Adjustable voltage version) V OUT dVdt + C OUT 80kW o (R 1 ) R 2) o R LOAD (5) REVERSE CURRENT The NMOS pass element of the TPS731xx provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. Copyright (c) 2003-2009, Texas Instruments Incorporated After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be additional current flowing into the OUT pin due to the 80k internal resistor divider to ground (see Figure 1 and Figure 2). For the TPS73101, reverse current may flow when VFB is more than 1.0V above VIN. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +160C, allowing the device to cool. When the junction temperature cools to approximately +140C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35C above the maximum expected ambient condition of your application. This produces a worst-case junction temperature of +125C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS731xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS731xx into thermal shutdown degrades device reliability. Submit Documentation Feedback 13 TPS731xx SBVS034M - SEPTEMBER 2003 - REVISED AUGUST 2009 .......................................................................................................................................... www.ti.com POWER DISSIPATION P D + (VIN * VOUT) I OUT The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Power Dissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heat-sink effectiveness. Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. (6) PACKAGE MOUNTING Solder pad footprint recommendations for the TPS731xx are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments web site at www.ti.com. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT): space REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (May, 2009) to Revision M ..................................................................................................... Page * * * 14 Changed Figure 12 ............................................................................................................................................................... 7 Added paragraph about recommended start-up sequence to Internal Current Limit section ............................................. 12 Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section ................................ 12 Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS73101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73101DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73101DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS731125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS731125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS731125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS731125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73115DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73118DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73130DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73131DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS73131DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73131DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73131DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73132DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73133DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73150DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2009 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS73101, TPS731125, TPS73115, TPS73118, TPS73125, TPS73130, TPS73132, TPS73133, TPS73150 : Product: TPS73101-EP, TPS731125-EP, TPS73115-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP, TPS73132-EP, * Enhanced TPS73133-EP, TPS73150-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS73101DBVR SOT-23 DBV 5 3000 178.0 9.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 TPS73101DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS731125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS731125DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73115DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73115DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73118DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73118DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73125DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73130DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73130DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73131DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73131DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73132DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73132DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73133DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73133DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS73150DBVR SOT-23 DBV 5 3000 178.0 9.0 TPS73150DBVT SOT-23 DBV 5 250 178.0 9.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73101DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73101DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS731125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS731125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73115DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73115DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73118DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73118DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73130DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73130DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73131DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73131DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73132DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73132DBVT SOT-23 DBV 5 250 203.0 203.0 35.0 TPS73133DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73133DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73150DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73150DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP(R) Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IF and ZigBee(R) Solutions www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2011, Texas Instruments Incorporated