Detailed Description
The MAX14986 consists of two identical redrivers with
input equalization and output preemphasis useful for SAS
or SATA signals up to 6.0GT/s.
Input/Output Terminations
Inputs and outputs are internally 50Ω terminated to VCC
(see the Functional Diagram) and must be AC-coupled
using 12nF (max) capacitors to the SAS/SATA controller
IC and SAS/SATA device for proper operation.
Enable Input (EN)
The MAX14986 features an active-high enable input (EN).
EN has an internal pulldown resistor of 70kΩ (typ). When
EN is driven low or left unconnected, the MAX14986
enters low-power standby mode and the redrivers are
disabled. Drive EN high for normal operation.
Out-of-Band Threshold Selector (MODE)
The MAX14986 provides full OOB signal support through
high-speed amplitude detection circuitry. OOB differential
input signals less than the internal OOB threshold (VSQ-
DIFF) are detected as off and not passed to the output.
This prevents the system from responding to unwanted
noise. OOB differential input signals higher than VSQ-
DIFF are detected as on and passed to the output, allow-
ing OOB signals to transmit through the MAX14986. The
logic level of the MODE input sets VSQ-DIFF for either
SAS or SATA OOB signals (see Table 1). MODE has an
internal pulldown resistor of 70kΩ (typ).
Input Equalization (EQ0, EQ1)
The MAX14986 features control logic inputs (EQ0, EQ1)
to enable input equalization on either channel, providing
3dB of boost (see Note 4 in the Electrical Characteristics
table). Drive EQ0 or EQ1 high to enable input equaliza-
tion on channel 0 or channel 1. Drive EQ0 or EQ1 low to
disable input equalization on channel 0 or channel 1 (see
Table 2). EQ0 and EQ1 have internal pulldown resistors
of 70kΩ (typ).
Output Preemphasis (PE0, PE1)
The MAX14986 features control logic inputs (PE0, PE1)
to enable output preemphasis on either channel, provid-
ing 3dB of boost. The MAX14986 uses true preemphasis,
so the transition signal is increased after a changing bit,
thus increasing the total energy content of the signal
when employed. Drive PE0 or PE1 high to enable output
preemphasis on channel 0 or channel 1. Drive PE0 or
PE1 low to disable output preemphasis on channel 0 or
channel 1 (see Table 3). PE0 and PE1 have internal pull-
down resistors of 70kΩ (typ).
Table 1. Out-of-Band Logic Threshold
(MODE)
Table 2. Input Equalization (EQ0, EQ1)
Table 3. Output Preemphasis (PE0, PE1)
PE1 PE0 CHANNEL 1
(dB)
CHANNEL 0
(dB)
0 0 0 0
0 1 0 3 (typ)
1 0 3 (typ) 0
1 1 3 (typ) 3 (typ)
EQ1 EQ0 CHANNEL 1
(dB)
CHANNEL 0
(dB)
0 0 0 0
0 1 0 3 (typ)
1 0 3 (typ) 0
1 1 3 (typ) 3 (typ)
MODE OOB MODE
0 SAS
1SATA
www.maximintegrated.com Maxim Integrated
│
9
MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation