TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DTrimmed Offset Voltage:
TLC277 . . . 500 µV Max at 25°C,
VDD = 5 V
DInput Offset Voltage Drift ...Typically
0.1 µV/Month, Including the First 30 Days
DWide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C...3 V to 16 V
–40°C to 85°C...4 V to 16 V
–55°C to 125°C...4 V to 16 V
DSingle-Supply Operation
DCommon-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix types)
DLow Noise ...Typically 25 nV/√Hz at
f = 1 kHz
DOutput Voltage Range Includes Negative
Rail
DHigh Input impedance ...10
12 Ω Typ
DESD-Protection Circuitry
DSmall-Outline Package Option Also
Available in Tape and Reel
DDesigned-In Latch-Up Immunity
description
The TLC272 and TLC277 precision dual
operational amplifiers combine a wide range of
input offset voltage grades with low of fset voltage
drift, high input impedance, low noise, and speeds
approaching those of general-purpose BiFET
devices.
These devices use Texas Instruments silicon-
gate LinCMOS technology, which provides
offset voltage stability far exceeding the stability
available with conventional metal-gate pro-
cesses.
The extremely high input impedance, low bias
currents, and high slew rates make these cost-
effective devices ideal for applications previously
reserved for BiFET and NFET products. Four
offset voltage grades are available (C-suffix and
I-suffix types), ranging from the low-cost TLC272
(10 mV) to the high-precision TLC277 (500 µV).
These advantages, in combination with good
common-mode rejection and supply voltage
rejection, make these devices a good choice for
new state-of-the-art designs as well as for
upgrading existing designs.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
GND
VDD
2OUT
2IN–
2IN+
D, JG, P, OR PW PACKAGE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN–
NC
NC
1IN–
NC
1IN+
NC
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
2IN +
NC NC
NC
GND
NC
NC – No internal connection
P Package
TA = 25°C
25
20
15
10
5
4000–400
0800
30
VIO – Input Offset Voltage – µV
Percentage of Units – %
–800
DISTRIBUTION OF TLC277
INPUT OFFSET VOLTAGE
VDD
473 Units Tested From 2 Wafer Lots
VDD = 5 V
(TOP VIEW)
LinCMOS is a trademark of Texas Instruments.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
TAVIOmax
AT 25°CSMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CHIP
FORM
(Y)
500
µ
VTLC277CD — — TLC277CP — —
0°Cto70°c
500
µV
2 mV
TLC277CD
TLC272BCD —
——
—
TLC277CP
TLC272BCP —
——
—
0°C to 70°c
2
mV
5 mV
TLC272BCD
TLC272ACD — —
TLC272BCP
TLC272ACP — —
5
mV
10mV
TLC272ACD
TLC272CD — —
TLC272ACP
TLC272CP TLC272CPW TLC272Y
500
µ
VTLC277ID — — TLC277IP — —
40°Cto85°C
500
µV
2 mV
TLC277ID
TLC272BID —
——
—
TLC277IP
TLC272BIP —
——
—
–40°C to 85°C
2
mV
5 mV
TLC272BID
TLC272AID — —
TLC272BIP
TLC272AIP — —
5
mV
10 mV
TLC272AID
TLC272ID — —
TLC272AIP
TLC272IP — —
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC277CDR).
In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC272 and
TLC277. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote
and inaccessible battery-powered applications. The common-mode input voltage range includes the negative
rail.
A wide range of packaging options is available, including small-outline and chip carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up.
The TLC272 and TLC277 incorporate internal ESD-protection circuits that prevent functional failures at voltages
up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling
these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from –40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of –55°C to 125°C.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent schematic (each amplifier)
P5 P6
OUT
N7N6
R7
N4
C1
R5
N3
GND
N2 D2R4D1R3
N1
IN+
IN–
P1
R1
P2
R2 N5
R6
P3 P4
VDD
TLC272Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC272C. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
+
–1OUT
1IN+
1IN–
VDD
(8)
(6)
(3)
(2)
(5)
(1)
–
+
(7) 2IN+
2IN–
2OUT
(4)
GND
60
73
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) –0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
output current, IO (each output) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD 45 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND 45 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package 260°C. . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN–.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW N/A
FK 1375 mW 11 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
P1000 mW 8.0 mW/°C 640 mW 520 mW N/A
PW 525 mW 4.2 mW/°C336 mW N/A N/A
recommended operating conditions
C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX UNIT
Supply voltage, VDD 3 16 4 16 4 16 V
Common mode input voltage V
VDD = 5 V –0.2 3.5 –0.2 3.5 0 3.5
V
Common-mode input voltage, VIC VDD = 10 V –0.2 8.5 –0.2 8.5 0 8.5 V
Operating free-air temperature, TA0 70 –40 85 –55 125 °C
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
†TLC272C, TLC272AC,
TLC272BC, TLC277C UNIT
TEST
CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC272C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC272C
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 12
mV
TLC272AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5 mV
V
Input offset voltage
TLC272AC
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 6.5
VIO Input offset voltage
TLC272BC
V
O
= 1.4 V, V
IC
= 0, 25°C 230 2000
TLC272BC
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 3000
V
TLC277C
V
O
= 1.4 V, V
IC
= 0, 25°C 200 500 µV
TLC277C
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 1500
αVIO Temperature coef ficient of input offset voltage 25°C to
70°C1.8 µV/°C
I
Input offset current (see Note 4)
25°C 0.1 60
pA
IIO Input of fset current (see Note 4)
V25V
V25V
70°C 7 300 pA
I
Input bias current (see Note 4)
VO = 2.5 V, VIC = 2.5 V 25°C0.6 60
pA
IIB Input bias current (see Note 4) 70°C 40 600 pA
V
Common-mode input volta
g
e ran
g
e25°C–0.2
to
4
–0.3
to
4.2 V
VICR
Common mode
in ut
voltage
range
(see Note 5) Full range –0.2
to
3.5 V
25°C 3.2 3.8
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ0°C3 3.8 V
VOH
High level
out ut
voltage
VID
100
mV,
RL
10
kΩ
70°C 3 3.8
V
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
VOL
Low level
out ut
voltage
VID
100
mV,
IOL
0
70°C 0 50
mV
25°C 5 23
AVD Large-signal differential voltage amplification VO = 0.25 V to 2 V, RL = 10 kΩ0°C4 27 V/mV
AVD
Large signal
differential
voltage
am lification
VO
0.25
V
to
2
V,
RL
10
kΩ
70°C 4 20
V/mV
25°C 65 80
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 84 dB
CMRR
Common mode
rejection
ratio
VIC
VICRmin
70°C 60 85
dB
S l lt j ti ti
25°C 65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V, VO = 1.4 V 0°C 60 94 dB
kSVR
(∆V
DD
/∆V
IO
)
VDD
5
V
to
10
V,
VO
1.4
V
70°C 60 96
dB
V25V
V25V
25°C 1.4 3.2
IDD Supply current (two amplifiers) VO = 2.5 V,
No load
VIC = 2.5 V, 0°C1.6 3.6 mA
DD
y( )
N
o
l
oa
d
70°C 1.2 2.6
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
†TLC272C, TLC272AC,
TLC272BC, TLC277C UNIT
PARAMETER
TEST
CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC272C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC272C
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 12
mV
TLC272AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5 mV
V
Input offset voltage
TLC272AC
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 6.5
VIO Input offset voltage
TLC272BC
V
O
= 1.4 V, V
IC
= 0, 25°C 290 2000
TLC272BC
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 3000
V
TLC277C
V
O
= 1.4 V, V
IC
= 0, 25°C 250 800 µV
TLC277C
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 1900
αVIO Temperature coef ficient of input offset voltage 25°C to
70°C2µV/°C
I
Input offset current (see Note 4)
25°C 0.1 60
pA
IIO Input of fset current (see Note 4)
V5V
V5V
70°C 7 300 pA
I
Input bias current (see Note 4)
VO = 5 V, VIC = 5 V 25°C0.7 60
pA
IIB Input bias current (see Note 4) 70°C 50 600 pA
V
Common-mode input volta
g
e ran
g
e25°C–0.2
to
9
–0.3
to
9.2 V
VICR
Common mode
in ut
voltage
range
(see Note 5) Full range –0.2
to
8.5 V
25°C 8 8.5
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ0°C7.8 8.5 V
VOH
High level
out ut
voltage
VID
100
mV,
RL
10
kΩ
70°C 7.8 8.4
V
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
VOL
Low level
out ut
voltage
VID
100
mV,
IOL
0
70°C 0 50
mV
25°C 10 36
AVD Large-signal differential voltage amplification VO = 1 V to 6 V, RL = 10 kΩ0°C7.5 42 V/mV
AVD
Large signal
differential
voltage
am lification
VO
1
V
to
6
V,
RL
10
kΩ
70°C 7.5 32
V/mV
25°C 65 85
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 88 dB
CMRR
Common mode
rejection
ratio
VIC
VICRmin
70°C 60 88
dB
S l lt j ti ti
25°C 65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V, VO = 1.4 V 0°C 60 94 dB
kSVR
(∆V
DD
/∆V
IO
)
VDD
5
V
to
10
V,
VO
1.4
V
70°C 60 96
dB
V5V
V5V
25°C 1.9 4
IDD Supply current (two amplifiers) VO = 5 V,
No load
VIC = 5 V, 0°C2.3 4.4 mA
DD
y( )
N
o
l
oa
d
70°C 1.6 3.4
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
†TLC272I, TLC272AI,
TLC272BI, TLC277I UNIT
TEST
CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC272I
V
O
= 1.4 V, V
IC
= 0, 25°C1.1 10
TLC272I
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 13
mV
TLC272AI
V
O
= 1.4 V, V
IC
= 0, 25°C0.9 5 mV
V
Input offset voltage
TLC272AI
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 7
VIO Input offset voltage
TLC272BI
V
O
= 1.4 V, V
IC
= 0, 25°C230 2000
TLC272BI
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 3500
V
TLC277I
V
O
= 1.4 V, V
IC
= 0, 25°C200 500 µV
TLC277I
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 2000
αVIO Temperature coef ficient of input offset voltage 25°C to
85°C1.8 µV/°C
I
Input offset current (see Note 4)
25°C0.1 60
pA
IIO Input of fset current (see Note 4)
V25V
V25V
85°C24 15 pA
I
Input bias current (see Note 4)
VO = 2.5 V, VIC = 2.5 V 25°C0.6 60
pA
IIB Input bias current (see Note 4) 85°C200 35 pA
V
Common-mode input volta
g
e ran
g
e25°C–0.2
to
4
–0.3
to
4.2 V
VICR
Common mode
in ut
voltage
range
(see Note 5) Full range –0.2
to
3.5 V
25°C3.2 3.8
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ–40°C3 3.8 V
VOH
High level
out ut
voltage
VID
100
mV,
RL
10
kΩ
85°C3 3.8
V
25°C0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 –40°C0 50 mV
VOL
Low level
out ut
voltage
VID
100
mV,
IOL
0
85°C0 50
mV
L i l diff ti l lt lifi ti
25°C5 23
AVD Large-signal differential voltage amplification VO = 1 V to 6 V, RL = 10 kΩ–40°C3.5 32 V/mV
AVD
VO
1
V
to
6
V,
RL
10
kΩ
85°C3.5 19
V/mV
25°C65 80
CMRR Common-mode rejection ratio VIC = VICRmin –40°C60 81 dB
CMRR
Common mode
rejection
ratio
VIC
VICRmin
85°C60 86
dB
S l lt j ti ti
25°C65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V, VO = 1.4 V –40°C60 92 dB
kSVR
(∆V
DD
/∆V
IO
)
VDD
5
V
to
10
V,
VO
1.4
V
85°C60 96
dB
V25V
V25V
25°C1.4 3.2
IDD Supply current (two amplifiers) VO = 2.5 V,
No load
VIC = 2.5 V, –40°C1.9 4.4 mA
DD
y( )
N
o
l
oa
d
85°C1.1 2.4
†Full range is –40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
†TLC272I, TLC272AI,
TLC272BI, TLC277I UNIT
PARAMETER
TEST
CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC272I
V
O
= 1.4 V, V
IC
= 0, 25°C1.1 10
TLC272I
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 13
mV
TLC272AI
V
O
= 1.4 V, V
IC
= 0, 25°C0.9 5 mV
V
Input offset voltage
TLC272AI
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 7
VIO Input offset voltage
TLC272BI
V
O
= 1.4 V, V
IC
= 0, 25°C290 2000
TLC272BI
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 3500
V
TLC277I
V
O
= 1.4 V, V
IC
= 0, 25°C250 800 µV
TLC277I
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 2900
αVIO Temperature coef ficient of input offset voltage 25°C to
85°C2µV/°C
I
Input offset current (see Note 4)
25°C0.1 60
pA
IIO Input of fset current (see Note 4)
V5V
V5V
85°C26 1000 pA
I
Input bias current (see Note 4)
VO = 5 V, VIC = 5 V 25°C0.7 60
pA
IIB Input bias current (see Note 4) 85°C220 2000 pA
V
Common-mode input volta
g
e ran
g
e25°C–0.2
to
9
–0.3
to
9.2 V
VICR
Common mode
in ut
voltage
range
(see Note 5) Full range –0.2
to
8.5 V
25°C8 8.5
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ–40°C7.8 8.5 V
VOH
High level
out ut
voltage
VID
100
mV,
RL
10
kΩ
85°C7.8 8.5
V
25°C0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 –40°C0 50 mV
VOL
Low level
out ut
voltage
VID
100
mV,
IOL
0
85°C0 50
mV
25°C10 36
AVD Large-signal differential voltage amplification VO = 1 V to 6 V, RL = 10 kΩ–40°C7 46 V/mV
AVD
Large signal
differential
voltage
am lification
VO
1
V
to
6
V,
RL
10
kΩ
85°C7 31
V/mV
25°C65 85
CMRR Common-mode rejection ratio VIC = VICRmin –40°C60 87 dB
CMRR
Common mode
rejection
ratio
VIC
VICRmin
85°C60 88
dB
S l lt j ti ti
25°C65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V, VO = 1.4 V –40°C60 92 dB
kSVR
(∆V
DD
/∆V
IO
)
VDD
5
V
to
10
V,
VO
1.4
V
85°C60 96
dB
V5V
V5V
25°C1.4 4
IDD Supply current (two amplifiers) VO = 5 V,
No load
VIC = 5 V, –40°C2.8 5 mA
DD
y( )
N
o
l
oa
d
85°C1.5 3.2
†Full range is –40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC272M, TLC277M
UNIT
PARAMETER TEST CONDITIONS TA
†
MIN TYP MAX UNIT
TLC272M
V
O
= 1.4 V, V
IC
= 0, 25°C1.1 10
mV
V
Input offset voltage
TLC272M
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 12 mV
VIO Input offset voltage
TLC277M
V
O
= 1.4 V, V
IC
= 0, 25°C200 500
V
TLC277M
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩFull range 3750 µV
αVIO Temperature coef ficient of input offset
voltage 25°C to
125°C2.1 µV/°C
I
Input offset current (see Note 4)
25°C0.1 60 pA
IIO Input of fset current (see Note 4)
V25V
V25V
125°C1.4 15 nA
I
Input bias current (see Note 4)
VO = 2.5 V VIC = 2.5 V 25°C0.6 60 pA
IIB Input bias current (see Note 4) 125°C9 35 nA
V
Common-mode input volta
g
e ran
g
e25°C0
to
4
–0.3
to
4.2 V
VICR
Common mode
in ut
voltage
range
(see Note 5) Full range 0
to
3.5 V
25°C3.2 3.8
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ–55°C3 3.8 V
VOH
High level
out ut
voltage
VID
100
mV,
RL
10
kΩ
125°C3 3.8
V
25°C0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 –55°C0 50 mV
VOL
Low level
out ut
voltage
VID
100
mV,
IOL
0
125°C0 50
mV
25°C5 23
AVD Large-signal differential voltage amplification VO = 0.25 V to 2 V RL = 10 kΩ–55°C3.5 35 V/mV
AVD
Large signal
differential
voltage
am lification
VO
0.25
V
to
2
V
RL
10
kΩ
125°C3.5 16
V/mV
25°C65 80
CMRR Common-mode rejection ratio VIC = VICRmin –55°C60 81 dB
CMRR
Common mode
rejection
ratio
VIC
VICRmin
125°C60 84
dB
S l lt j ti ti
25°C65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V, VO = 1.4 V –55°C60 90 dB
kSVR
(∆V
DD
/∆V
IO
)
VDD
5
V
to
10
V,
VO
1.4
V
125°C60 97
dB
V25V
V25V
25°C1.4 3.2
IDD Supply current (two amplifiers) VO = 2.5 V,
No load
VIC = 2.5 V, –55°C2 5 mA
DD
y( )
N
o
l
oa
d
125°C1 2.2
†Full range is –55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC272M, TLC277M
UNIT
PARAMETER TEST CONDITIONS TA
†
MIN TYP MAX UNIT
TLC272M
VO = 1.4 V, VIC = 0, 25°C 1.1 10
mV
V
Input offset voltage
TLC272M RS = 50 Ω, RL = 10 kΩFull range 12 mV
VIO Input offset voltage
TLC277M
VO = 1.4 V, VIC = 0, 25°C 250 800
V
TLC277M RS = 50 Ω, RL = 10 kΩFull range 4300 µV
αVIO Temperature coef ficient of input offset
voltage 25°C to
125°C2.2 µV/°C
I
Input offset current (see Note 4)
25°C 0.1 60 pA
IIO Input of fset current (see Note 4)
V5V
V5V
125°C 1.8 15 nA
I
Input bias current (see Note 4)
VO = 5 V, VIC = 5 V 25°C0.7 60 pA
IIB Input bias current (see Note 4) 125°C 10 35 nA
V
Common-mode input volta
g
e ran
g
e25°C0
to
9
–0.3
to
9.2 V
VICR
Common mode
in ut
voltage
range
(see Note 5) Full range 0
to
8.5 V
25°C 8 8.5
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ–55°C7.8 8.5 V
VOH
High level
out ut
voltage
VID
100
mV,
RL
10
kΩ
125°C 7.8 8.4
V
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 –55°C0 50 mV
VOL
Low level
out ut
voltage
VID
100
mV,
IOL
0
125°C 0 50
mV
L i l diff ti l lt
25°C 10 36
AVD Large-signal differential voltage
am
p
lification
VO = 1 V to 6 V, RL = 10 kΩ–55°C7 50 V/mV
AVD
amp
lifi
ca
ti
on
VO
1
V
to
6
V,
RL
10
kΩ
125°C 7 27
V/mV
25°C 65 85
CMRR Common-mode rejection ratio VIC = VICRmin –55°C 60 87 dB
CMRR
Common mode
rejection
ratio
VIC
VICRmin
125°C 60 86
dB
S l lt j ti ti
25°C 65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V, VO = 1.4 V –55°C60 90 dB
kSVR
(∆V
DD
/∆V
IO
)
VDD
5
V
to
10
V,
VO
1.4
V
125°C 60 97
dB
V5V
V5V
25°C 1.9 4
IDD Supply current (two amplifiers) VO = 5 V,
No load
VIC = 5 V, –55°C3 6 mA
DD
y( )
N
o
l
oa
d
125°C 1.3 2.8
†Full range is –55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC272Y
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Input offset voltage
V
O
= 1.4 V, V
IC
= 0,
11
10
mV
VIO Input offset voltage
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩ1.1 10 mV
αVIO Temperature coef ficient of input offset voltage 1.8 µV/°C
IIO Input of fset current (see Note 4)
V25V
V25V
0.1 pA
IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 0.6 pA
VICR Common-mode input voltage range (see Note 5) –0.2
to
4
–0.3
to
4.2 V
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ3.2 3.8 V
VOL Low-level output voltage VID = –100 mV, IOL = 0 0 50 mV
AVD Large-signal differential voltage amplification VO = 0.25 V to 2 V RL = 10 kΩ5 23 V/mV
CMRR Common-mode rejection ratio VIC = VICRmin 65 80 dB
kSVR Supply-voltage rejection ratio (∆VDD /∆VIO) VDD = 5 V to 10 V, VO = 1.4 V 65 95 dB
IDD Supply current (two amplifiers) VO = 2.5 V,
No load VIC = 2.5 V, 1.4 3.2 mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
electrical characteristics, VDD = 10 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC272Y
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Input offset voltage
V
O
= 1.4 V, V
IC
= 0,
11
10
mV
VIO Input offset voltage
VO
=
1
.
4
V
,
RS = 50 Ω,
VIC
=
0
,
RL = 10 kΩ1.1 10 mV
αVIO Temperature coef ficient of input offset voltage 1.8 µV/°C
IIO Input of fset current (see Note 4)
V5V
V5V
0.1 pA
IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 0.7 pA
VICR Common-mode input voltage range (see Note 5) –0.2
to
9
–0.3
to
9.2 V
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ8 8.5 V
VOL Low-level output voltage VID = –100 mV, IOL = 0 0 50 mV
AVD Large-signal differential voltage amplification VO = 1 V to 6 V, RL = 10 kΩ10 36 V/mV
CMRR Common-mode rejection ratio VIC = VICRmin 65 85 dB
kSVR Supply-voltage rejection ratio (∆VDD/∆VIO)VDD = 5 V to 10 V, VO = 1.4 V 65 95 dB
IDD Supply current (two amplifiers) VO = 5 V,
No load VIC = 5 V, 1.9 4 mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS T
A
TLC272C, TLC272AC,
TLC272BC, TLC277C UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX
UNIT
25°C3.6
VIPP = 1 V 0°C4
SR
Slew rate at unity gain
RL = 10 kΩ,
C20pF
VIPP
1
V
70°C3
V/ s
SR Slew rate at unity gain CL = 20 pF,
See Figure 1
25°C2.9 V/µs
See
Fig
u
re
1
VIPP = 2.5 V 0°C3.1
VIPP
2.5
V
70°C2.5
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C25 nV/√Hz
VV
C20F
25°C320
BOM Maximum output-swing bandwidth VO = VOH,
RL=10kΩ
CL = 20 pF,
See Figure 1
0°C340 kHz
BOM
Maximum
out ut swing
bandwidth
R
L =
10
kΩ
,
S
ee
Fi
gure
1
70°C260
kHz
V10V
C20F
25°C1.7
B1Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, 0°C2MHz
B1
Unity gain
bandwidth
S
ee
Fi
gure
3
70°C1.3
MHz
V10V
fB
25°C 46°
φmPhase margin VI = 10 mV,
CL=20
p
F
f = B1,
See Figure 3
0°C 47°
φm
g
C
L =
20
p
F
,
S
ee
Fi
gure
3
70°C 43°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS T
A
TLC272C, TLC272AC,
TLC272BC, TLC277C UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX
UNIT
25°C5.3
VIPP = 1 V 0°C5.9
SR
Slew rate at unity gain
RL = 10 kΩ,
C20pF
VIPP
1
V
70°C4.3
V/ s
SR Slew rate at unity gain CL = 20 pF,
See Figure 1
25°C4.6 V/µs
See
Fig
u
re
1
VIPP = 5.5 V 0°C5.1
VIPP
5.5
V
70°C3.8
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C25 nV/√Hz
VV
C20F
25°C200
BOM Maximum output-swing bandwidth VO = VOH,
RL=10kΩ
CL = 20 pF,
See Figure 1
0°C220 kHz
BOM
Maximum
out ut swing
bandwidth
R
L =
10
kΩ
,
S
ee
Fi
gure
1
70°C140
kHz
V10V
C20F
25°C2.2
B1Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, 0°C2.5 MHz
B1
Unity gain
bandwidth
S
ee
Fi
gure
3
70°C1.8
MHz
V10V
fB
25°C 49°
φmPhase margin VI = 10 mV,
CL=20
p
F
f = B1,
See Figure 3
0°C 50°
φm
g
C
L =
20
p
F
,
S
ee
Fi
gure
3
70°C 46°
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS T
A
TLC272I, TLC272AI,
TLC272BI, TLC277I UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX
UNIT
25°C3.6
VIPP = 1 V –40°C4.5
SR
Slew rate at unity gain
RL = 10 kΩ,
C20pF
VIPP
1
V
85°C2.8
V/ s
SR Slew rate at unity gain CL = 20 pF,
See Figure 1
25°C2.9 V/µs
See
Fig
u
re
1
VIPP = 2.5 V –40°C3.5
VIPP
2.5
V
85°C2.3
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C25 nV/√Hz
VV
C20F
25°C320
BOM Maximum output-swing bandwidth VO = VOH,
RL=10kΩ
CL = 20 pF,
See Figure 1
–40°C380 kHz
BOM
Maximum
out ut swing
bandwidth
R
L =
10
kΩ
,
S
ee
Fi
gure
1
85°C250
kHz
V10V
C20F
25°C1.7
B1Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, –40°C2.6 MHz
B1
Unity gain
bandwidth
S
ee
Fi
gure
3
85°C1.2
MHz
V10V
fB
25°C 46°
φmPhase margin VI = 10 mV,
CL=20
p
F
f = B1,
See Figure 3
–40°C 49°
φm
g
C
L =
20
p
F
,
S
ee
Fi
gure
3
85°C 43°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS T
A
TLC272I, TLC272AI,
TLC272BI, TLC277I UNIT
PARAMETER
TEST
CONDITIONS
TA
MIN TYP MAX
UNIT
25°C5.3
VIPP = 1 V –40°C6.8
SR
Slew rate at unity gain
RL = 10 kΩ,
C20pF
VIPP
1
V
85°C4
V/ s
SR Slew rate at unity gain CL = 20 pF,
See Figure 1
25°C4.6 V/µs
See
Fig
u
re
1
VIPP = 5.5 V –40°C5.8
VIPP
5.5
V
85°C3.5
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C25 nV/√Hz
VV
C20F
25°C200
BOM Maximum output-swing bandwidth VO = VOH,
RL=10kΩ
CL = 20 pF,
See Figure 1
–40°C260 kHz
BOM
Maximum
out ut swing
bandwidth
R
L =
10
kΩ
,
S
ee
Fi
gure
1
85°C130
kHz
V10V
C20F
25°C2.2
B1Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, –40°C3.1 MHz
B1
Unity gain
bandwidth
S
ee
Fi
gure
3
85°C1.7
MHz
V10V
fB
25°C 49°
φmPhase margin VI = 10 mV,
CL=20
p
F
f = B1,
See Figure 3
–40°C 52°
φm
g
C
L =
20
p
F
,
S
ee
Fi
gure
3
85°C 46°
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC272M, TLC277M
UNIT
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
25°C3.6
VIPP = 1 V –55°C4.7
SR
Slew rate at unity gain
RL = 10 kΩ,
C20pF
VIPP
1
V
125°C2.3
V/ s
SR Slew rate at unity gain CL = 20 pF,
See Figure 1
25°C2.9 V/µs
See
Fig
u
re
1
VIPP = 2.5 V –55°C3.7
VIPP
2.5
V
125°C2
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C25 nV/√Hz
VV
C20F
25°C320
BOM Maximum output-swing bandwidth VO = VOH,
RL=10kΩ
CL = 20 pF,
See Figure 1
–55°C400 kHz
BOM
Maximum
out ut swing
bandwidth
R
L =
10
kΩ
,
S
ee
Fi
gure
1
125°C230
kHz
V10V
C20F
25°C1.7
B1Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, –55°C2.9 MHz
B1
Unity gain
bandwidth
S
ee
Fi
gure
3
125°C1.1
MHz
V10V
fB
25°C 46°
φmPhase margin VI = 10 mV,
CL=20
p
F
f = B1,
See Figure 3
–55°C 49°
φm
g
C
L =
20
p
F
,
S
ee
Fi
gure
3
125°C 41°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC272M, TLC277M
UNIT
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
25°C5.3
VIPP = 1 V –55°C7.1
SR
Slew rate at unity gain
RL = 10 kΩ,
C20pF
VIPP
1
V
125°C3.1
V/ s
SR Slew rate at unity gain CL = 20 pF,
See Figure 1
25°C4.6 V/µs
See
Fig
u
re
1
VIPP = 5.5 V –55°C6.1
VIPP
5.5
V
125°C2.7
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C25 nV/√Hz
VV
C20F
25°C200
BOM Maximum output-swing bandwidth VO = VOH,
RL=10kΩ
CL = 20 pF,
See Figure 1
–55°C280 kHz
BOM
Maximum
out ut swing
bandwidth
R
L =
10
kΩ
,
S
ee
Fi
gure
1
125°C110
kHz
V10V
C20F
25°C2.2
B1Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, –55°C3.4 MHz
B1
Unity gain
bandwidth
S
ee
Fi
gure
3
125°C1.6
MHz
V10V
fB
25°C 49°
φmPhase margin VI = 10 mV,
CL=20
p
F
f = B1,
See Figure 3
–55°C 52°
φm
g
C
L =
20
p
F
,
S
ee
Fi
gure
3
125°C 44°
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC272Y
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Slew rate at unity gain
R
L
= 10 kΩ,C
L
= 20 pF, VIPP = 1 V 3.6
V/ s
SR Slew rate at unity gain
RL
=
10
kΩ
,
See Figure 1
CL
=
20
F
,VIPP = 2.5 V 2.9 V/µs
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25 nV/√Hz
BOM Maximum output-swing bandwidth VO = VOH,
See Figure 1 CL = 20 pF, RL = 10 kΩ,320 kHz
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 1.7 MHz
φmPhase margin VI = 10 mV,
See Figure 3 f = B1, CL = 20 pF, 46°
operating characteristics, VDD = 10 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC272Y
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Slew rate at unity gain
R
L
= 10 kΩ,C
L
= 20 pF, VIPP = 1 V 5.3
V/ s
SR Slew rate at unity gain
RL
=
10
kΩ
,
See Figure 1
CL
=
20
F
,VIPP = 5.5 V 4.6 V/µs
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25 nV/√Hz
BOM Maximum output-swing bandwidth VO = VOH,
See Figure 1 CL = 20 pF, RL = 10 kΩ,200 kHz
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 2.2 MHz
φmPhase margin VI = 10 mV,
See Figure 3 f = B1, CL = 20 pF, 49°
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC272 and TLC277 are optimized for single-supply operation, circuit configurations used for the
various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either
circuit gives the same result.
VDD–
VDD+
–
+
CLRL
VO
VI
VI
VO
RL
CL
VDD
–
+
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
VO
2 kΩ
20 Ω20 Ω
VDD–
20 Ω
2 kΩ
VO
20 Ω
1/2 VDD
–
+
VDD+
–
+
VDD
(b) SPLIT SUPPLY
(a) SINGLE SUPPLY
Figure 2. Noise-Test Circuit
VDD–
VDD+
–
+
10 kΩ
VO
100 Ω
CL
VI
VI
1/2 VDD CL
100 Ω
VO
10 kΩ
–
+
VDD
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC272 and TLC277 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature
is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. T wo suggestions are
offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
85
14
V = VIC
Figure 4. Isolation Metal Around Device Inputs
(JG and P packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on the common-mode input voltage level as well as the
differential input voltage level. When attempting to correlate low-level output readings with those quoted in the
electrical specifications, these two conditions should be observed. If conditions other than these are to be used,
please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input of fset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(d) f > BOM
(c) f = BOM
(b) BOM > f > 1 kHz(a) f = 1 kHz
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input of fset voltage Distribution 6, 7
αVIO Temperature coef ficient of input offset voltage Distribution 8, 9
vs Hi
g
h-level output current 10
,
11
V
OH
Hi
g
h-level output volta
g
e
vs
High
-
level
out ut
current
vs Supply voltage
10
,
11
12
VOH
High level
out ut
voltage
vs
Su ly
voltage
vs Free-air temperature
12
13
vs Common-mode input volta
g
e 14
,
15
V
Low level output voltage
vs
Common
-
mode
in ut
voltage
vs Differential input volta
g
e
14
,
15
16
VOL Low-level output voltage
vs
Differential
in ut
voltage
vs Free-air temperature
16
17
vs
Free air
tem erature
vs Low-level output current
17
18, 19
vs Suppl
y
volta
g
e 20
A
VD
Lar
g
e-si
g
nal differential volta
g
e amplification
vs
Su ly
voltage
vs Free-air temperature
20
21
AVD
Large signal
differential
voltage
am lification
vs
Free air
tem erature
vs Frequency
21
32, 33
IIB Input bias current vs Free-air temperature 22
IIO Input offset current vs Free-air temperature 22
VIC Common-mode input voltage vs Supply voltage 23
I
Supply current
vs Supply volta
g
e 24
IDD Supply current
vs
Su ly
voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Suppl
y
volta
g
e 26
SR Slew rate
vs
Su ly
voltage
vs Free-air temperature
26
27
Normalized slew rate vs Free-air temperature 28
VO(PP) Maximum peak-to-peak output voltage vs Frequency 29
B
Unity gain bandwidth
vs Free-air temperature 30
B1Unity-gain bandwidth
vs
Free air
tem erature
vs Supply voltage
30
31
vs Suppl
y
volta
g
e 34
φm
Phase mar
g
in
vs
Su ly
voltage
vs Free-air temperature
34
35
φm
Phase
margin
vs
Free air
tem erature
vs Load capacitance
35
36
VnEquivalent input noise voltage vs Frequency 37
Phase shift vs Frequency 32, 33
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
–5
0
Percentage of Units – %
VIO – Input Offset Voltage – mV 5
60
–4–3–2–101234
10
20
30
40
50
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
753 Amplifiers Tested From 6 Wafer Lots
ÌÌÌÌ
ÌÌÌÌ
VDD = 5 V
ÌÌÌÌÌ
ÌÌÌÌÌ
TA = 25°C
ÌÌÌÌÌ
ÌÌÌÌÌ
P Package
DISTRIBUTION OF TLC272
INPUT OFFSET VOLTAGE
Figure 7
50
40
30
20
10
43210–1–2–3–4
60
5
VIO – Input Offset Voltage – mV
Percentage of Units – %
0–5
DISTRIBUTION OF TLC272
INPUT OFFSET VOLTAGE
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
753 Amplifiers Tested From 6 Wafer Lots
ÌÌÌÌ
VDD = 10 V
ÌÌÌÌ
ÌÌÌÌ
TA = 25°C
ÌÌÌÌ
ÌÌÌÌ
P Package
Figure 8
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
324 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 20.5 µV/°C
50
40
30
20
10
864
20–2–4–6–8
60
10
Percentage of Units – %
0
–10 αVIO – Temperature Coefficient – µV/°C
DISTRIBUTION OF TLC272 AND TLC277
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
Figure 9
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
324 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 21.2 µV/°C
–10
0
Percentage of Units – %
10
60
–8–6–4–202468
10
20
30
40
50
Á
αVIO – Temperature Coefficient – µV/°C
DISTRIBUTION OF TLC272 AND TLC277
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
Á
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 10
VDD = 3 V
VDD = 4 V
VDD = 5 V
VID = 100 mV
TA = 25°C
See Note A
4
3
2
1
–8–6–4–2
5
–10
IOH – High-Level Output Current – mA
VOH – High-Level Output Voltage – V
00
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOH
NOTE A: The 3-V curve only applies to the C version.
Figure 11
TA = 25°C
VID = 100 mV
VDD = 10 V
VDD = 16 V
14
12
10
8
6
4
2
–30–20–10
16
–40
IOH – High-Level Output Current – mA
VOH – High-Level Output Voltage – V
00
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOH
–5–15 –20 –25 –35
Figure 12
ÌÌÌÌÌ
TA = 25°C
ÌÌÌÌ
ÌÌÌÌ
RL = 10 kΩ
ÌÌÌÌÌ
VID = 100 mV
0
16
2
4
6
8
10
12
14
1412108642 16
VDD – Supply Voltage – V
0
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
VOH – High-Level Output Voltage – V
ÁÁ
ÁÁ
ÁÁ
VOH
Figure 13
VDD = 10 V
VDD = 5 V VID = 100 mA
IOH = –5 mA
–75 TA – Free-Air Temperature – °C125
VDD –1.6
–50 –25 0 20 50 75 100
VDD –1.8
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VDD –1.7
VDD –1.9
VDD –2.1
VDD –2
VDD –2.3
VDD –2.2
VDD –2.4
VOH – High-Level Output Voltage – V
ÁÁ
ÁÁ
ÁÁ
VOH
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 14
VID = –1 V
VID = –100 mV
VDD = 5 V
IOL = 5 mA
TA = 25°C
600
500
400
321
700
4
VIC – Common-Mode Input Voltage – V
VOL – Low-Level Output Voltage – mV
300 0
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
ÁÁ
ÁÁ
ÁÁ
VOL
0.5 1.5 2.5 3.5
650
550
450
350
Figure 15
VID = –100 mV
VID = –2.5 V
VID = –1 V
TA = 25°C
IOL = 5 mA
VDD = 10 V
108642
500
450
400
350
300
VIC – Common-Mode Input Voltage – V
0
250
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VOL – Low-Level Output Voltage – mV
ÁÁ
ÁÁ
VOL
13579
Figure 16
VDD = 10 V
VDD = 5 V
TA = 25°C
VIC = |VID/2|
IOL = 5 mA
0
100
200
300
400
500
600
700
800
–8–6–4–2–10
VID – Differential Input Voltage – V
0
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
–1–3–5–7–9
VOL – Low-Level Output Voltage – mV
ÁÁ
ÁÁ
ÁÁ
VOL
Figure 17
VDD = 10 V
VDD = 5 V
IOL = 5 mA
VID = –1 V
VIC = 0.5 V
800
700
600
500
400
300
200
100
1007550250–25–50
900
125
TA – Free-Air Temperature – °C
0–75
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOL – Low-Level Output Voltage – mV
ÁÁ
ÁÁ
ÁÁ
VOL
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 18
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 5 V
VDD = 4 V
VDD = 3 V
ÌÌÌÌ
ÌÌÌÌ
TA = 25°C
See Note A
ÌÌÌÌ
ÌÌÌÌ
VIC = 0.5 V
ÌÌÌÌ
VID = –1 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
7654321
08
1.0
IOL – Low-Level Output Current – mA
VOL – Low-Level Output Voltage – V
0
ÁÁ
ÁÁ
VOL
NOTE A: The 3-V curve only applies to the C version. Figure 19
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 16 V
VDD = 10 V
ÌÌÌÌ
VID = –1 V
ÌÌÌÌÌ
ÌÌÌÌÌ
VIC = 0.5 V
ÌÌÌÌ
ÌÌÌÌ
TA = 25°C
2.5
2.0
1.5
1.0
0.5
252015105
030
3.0
IOL – Low-Level Output Current – mA
VOL – Low-Level Output Voltage – V
0
ÁÁ
ÁÁ
ÁÁ
VOL
Figure 20
0
60
16
02 4 6 8 10 12 14
10
20
30
40
50
VDD – Supply Voltage – V
TA = –55°C
RL = 10 kΩ
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
ÌÌÌÌ
ÌÌÌÌ
TA = 25°C
ÌÌÌÌ
TA = 85°C
ÌÌÌÌÌ
TA = 125°C
ÌÌÌÌ
TA = 0°C
AVD – Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
V oltage Amplification – V/mV
Figure 21
–75
50
125
0–50 –25 0 25 50 75 100
5
10
15
20
25
30
35
40
45
VDD = 5 V
VDD = 10 V
RL = 10 kΩ
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
AVD – Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
V oltage Amplification – V/mV
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 22
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
0.1 125
10000
45 65 85 105
1
10
100
1000
25
– Input Bias and Offset Currents – pA
VDD = 10 V
VIC = 5 V
See Note A
ÌÌ
IIB
IIB IIO
and
TA – Free-Air Temperature – °C
ÌÌ
ÌÌ
IIO
35 55 75 95 115
NOTE A: The typical values of input bias current and input
offset current below 5 pA were determined mathematically. Figure 23
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
0VDD – Supply Voltage – V
16
16
02 4 6 8 10 12 14
2
4
6
8
10
12
14 TA = 25°C
IC
V– Common-Mode Input Voltage – V
Figure 24
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0VDD – Supply Voltage – V
5
16
02 4 6 8 10 12 14
1
2
3
4
VO = VDD/2
No Load TA = –55°C
– Supply Current – mAIDD
0.5
1.5
2.5
3.5
4.5
ÌÌÌÌ
TA = 70°C
ÌÌÌÌ
ÌÌÌÌ
TA = 125°C
ÌÌÌ
TA = 0°C
ÌÌÌÌ
ÌÌÌÌ
TA = 25°C
Figure 25
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
–75
– Supply Current – mA
2
125
0
0.5
1
1.5
–50 –25 0 25 50 75 100
No Load
VO = VDD/2
VDD = 10 V
VDD = 5 V
2.5
3
3.5
4
IDD
TA – Free-Air Temperature – °C
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 26
AV = 1
VIPP = 1 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
See Figure 1
8
7
6
5
4
3
2
1
1412108642
016
VDD – Supply Voltage – V
0
SLEW RATE
vs
SUPPLY VOLTAGE
µsSR – Slew Rate – V/
Figure 27
VIPP = 1 V
VDD = 10 V
VIPP = 2.5 V
VDD = 5 V
VIPP = 1 V
VDD = 5 V
VDD = 10 V
VIPP = 5.5 V
–75
0
1
2
3
4
5
6
7
8
1007550250–25–50 125
TA – Free-Air Temperature – °C
SLEW RATE
vs
FREE-AIR TEMPERATURE
AV = 1
RL = 10 kΩ
CL = 20 pF
See Figure 1
µsSR – Slew Rate – V/
Figure 28
VDD = 5 V
VDD = 10 V
1.5
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
CL = 20 pF
RL = 10 kΩ
VIPP = 1 V
AV = 1
1007550250–25–50 125
TA – Free-Air Temperature – °C
Normalized Slew Rate
–75
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
Figure 29
TA = –55°C
TA = 25°C
TA = 125°C
RL = 10 kΩ
See Figure 1
VDD = 5 V
VDD = 10 V
1000100
9
8
7
6
5
4
3
2
1
010000
10
f – Frequency – kHz
10
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREQUENCY
– Maximum Peak-to-Peak Output Voltage – V
VO(PP)
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 30
2.5
2.0
1.5
1007550250–25–50
1.0
3.0
TA – Free-Air Temperature – °C
–75
See Figure 3
CL = 20 pF
VI = 10 mV
VDD = 5 V
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
– Unity-Gain Bandwidth – MHz
B1
125
Figure 31
2.0
1.5
1412108642
1.0 16
2.5
VDD – Supply Voltage – V
0
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
– Unity-Gain Bandwidth – MHz
B1
Phase Shift
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
Phase Shift
AVD
VDD = 5 V
RL = 10 kΩ
TA = 25°C
180°
0°
30°
60°
90°
120°
150°
106
105
104
103
102
101
1
1 M100 k10 k1 k100
0.1 10 M
f – Frequency – Hz
10
107
AVD – Large-Signal Differential
Á
Á
AVD V oltage Amplification
Figure 32
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Phase Shift
AVD
TA = 25°C
RL = 10 kΩ
VDD = 10 V
Phase Shift
150°
120°
90°
60°
30°
0°
180°
106
105
104
103
102
101
1
1 M100 k10 k1 k100
0.1 10 M
f – Frequency – Hz
10
107
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
AVD – Large-Signal Differential
ÁÁ
ÁÁ
AVD V oltage Amplification
Figure 33
Figure 34
45°
See Figure 3
VI = 10 mV
TA = 25°C
CL = 20 pF
51°
49°
47°
1412108642 16
53°
VDD – Supply Voltage – V
m – Phase Margin
0
PHASE MARGIN
vs
SUPPLY VOLTAGE
m
φ
48°
46°
52°
50°
Figure 35
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
See Figure 3
VI = 10 mV
CL = 20 pF
VDD = 5 V
48°
46°
44°
42°
1007550250–25–50
40°125
50°
–75
m – Phase Margin
m
φ
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
VDD = 5 V
TA = 25°C
VI = 10 mV
See Figure 3
45°
40°
35°
30°
80604020
25°100
50°
CL – Capacitive Load – pF
0
PHASE MARGIN
vs
CAPACITIVE LOAD
m – Phase Margin
m
φ
10 30 50 70 90
Figure 37
VN – Equivalent Input Noise Voltage –
See Figure 2
RS = 20 Ω
TA = 25°C
VDD = 5 V
10010
300
200
100
01000
400
f – Frequency – Hz
1
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
nV/ Hz
Vn
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
single-supply operation
While the TLC272 and TLC277 perform well using dual power supplies (also called balanced or split supplies),
the design is optimized for single-supply operation. This design includes an input common-mode voltage range
that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage
range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for
TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC272 and TLC277 permits the use of very large resistive values to implement
the voltage divider, thus minimizing power consumption.
The TLC272 and TLC277 work well in conjunction with digital logic; however, when powering both linear devices
and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
–
+
C
0.01 µF
R3
VREF
VI
R1 R2
VDD
VO
R4
VREF +VDD R3
R1 )R3
VO+(VREF *VI)R4
R2 )VREF
Figure 38. Inverting Amplifier With Voltage Reference
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
(a) COMMON SUPPLY RAILS
–
+
–
+
Logic Logic Logic Power
Supply
Supply
Power
LogicLogicLogic
OUT
OUT
Figure 39. Common vs Separate Supply Rails
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input characteristics
The TLC272 and TLC277 are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially
in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD – 1 V at TA = 25°C and at VDD – 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC272 and TLC277 very
good input offset voltage drift characteristics relative to conventional metal-gate processes. Of fset voltage drift
in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC272 and
TLC277 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good
practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC272 and TLC277 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.
VI
–
+
–
+
VI
(b) INVERTING AMPLIFIER
–
+
(c) UNITY-GAIN AMPLIFIER(a) NONINVERTING AMPLIFIER
VI
OUT OUT OUT
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC272 and TLC277 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC272 and TLC277 are measured using a 20-pF load. The devices can
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics (continued)
(c) CL = 150 pF, RL = NO LOAD
(b) CL = 130 pF, RL = NO LOAD
(a) CL = 20 pF, RL = NO LOAD
VI
–2.5 V
CL
VO
2.5 V
–
+
TA = 25°C
f = 1 kHz
VIPP = 1 V
(d) TEST CIRCUIT
Figure 41. Effect of Capacitive Loads and Test Circuit
Although the TLC272 and TLC277 possess excellent high-level output voltage and current capability , methods
for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor
(RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages to the
use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on resistance between
approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low
values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a drain load to
N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the
output current.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics (continued)
Figure 42. Resistive Pullup to Increase VOH
VDD – VO
IF + IL + IP
Rp =
IL
IF
IP
RL
R1 R2
VO
RP
VDD
VI
–
+
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Ip = Pullup current required by
the operational amplifier
(typically 500 µA)
Figure 43. Compensation for Input Capacitance
C
–
+
VO
feedback
Operational amplifier circuits almost always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically .
electrostatic discharge protection
The TLC272 and TLC277 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents
functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be
exercised, however, when handling these devices as exposure to ESD may result in the degradation of the
device parametric performance. The protection circuit also causes the input bias currents to be temperature
dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC272 and
TLC277 inputs and outputs were designed to withstand –100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
10 kΩ
10 kΩ
5 kΩ
VI
–
+
10 kΩ
10 kΩ
10 kΩ
0.016 µF
–
+
R = 5 kΩ(3/d-1) (see Note A) Band Pass
High Pass
Low Pass
–
+
0.016 µF
5 V
1/2
TLC272
1/2
TLC272 1/2
TLC272
NOTE A: d = damping factor, 1/Q
Figure 44. State-Variable Filter
1/2
TLC272
VI
12 V
H.P.
5082-2835
0.5 µF
Mylar
VO
100 kΩ
–
+
–
+
1/2
TLC272
N.O.
Reset
Figure 45. Positive-Peak Detector
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1/2
TLC272
110 Ω
VO
(see Note B)
–
+
250 µF,
25 V
10 kΩ
TIP31
TL431 20 kΩ1 kΩ
100 kΩ0.47 µF
15 Ω
TIS193
0.01 µF
47 kΩ
22 kΩ
0.1 µF
4.7 kΩ
1.2 kΩ
VI
(see Note A)
–
+
NOTES: A. VI = 3.5 to 15 V
B. VO = 2 V, 0 to 1 A
Figure 46. Logic-Array Power Supply
9 V
100 kΩ
47 kΩ
TLC272
1/2
1/2
TLC272 R2
VO (see Note A)
VO (see Note B)
10 kΩ
10 kΩ
R3
0.1 µF
100 kΩ
9 V
R1
–
+
fO+1
4C(R2)[R1
R3]
C
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
Figure 47. Single-Supply Function Generator
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUAR Y 2002
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
10 kΩ
1/2
TLC277
(see Note A)
R1,10 kΩ
VO
95 kΩ
10 kΩ
–
+
–5 V
VI+
VI–
5 V
10 kΩ100 kΩ
–
+
–
+1/2
TLC277
1/2
TLC277
NOTE B: CMRR adjustment must be noninductive.
Figure 48. Low-Power Instrumentation Amplifier
R/2
5 MΩ
C
270 pF
2C
540 pF
R
10 MΩVO
VI
5 V
–
+
fNOTCH +1
2pRC
C
270 pF
R
10 MΩ
1/2
TLC272
Figure 49. Single-Supply Twin-T Notch Filter
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or Sales Office
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TLC277IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TLC277IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2010
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC277MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI Samples Not Available
TLC277MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI Samples Not Available
TLC277MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC272ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC272AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC272BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC272BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC272CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC272CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TLC272CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC272IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC277CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC277CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TLC277IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC272ACDR SOIC D 8 2500 340.5 338.1 20.6
TLC272AIDR SOIC D 8 2500 340.5 338.1 20.6
TLC272BCDR SOIC D 8 2500 340.5 338.1 20.6
TLC272BIDR SOIC D 8 2500 340.5 338.1 20.6
TLC272CDR SOIC D 8 2500 340.5 338.1 20.6
TLC272CPSR SO PS 8 2000 367.0 367.0 38.0
TLC272CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLC272IDR SOIC D 8 2500 340.5 338.1 20.6
TLC277CDR SOIC D 8 2500 340.5 338.1 20.6
TLC277CPSR SO PS 8 2000 367.0 367.0 38.0
TLC277IDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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