R7731A
1
R7731A-10 August 2011 www.richtek.com
General Description
The R7731A is a high-performance, low cost, low start-up
current and current mode PWM controller with burst triple
mode to support green mode power saving operation. The
R7731A integrates functions of soft start, Under Voltage
LockOut (UVLO), Leading Edge Blanking (LEB), Over
Temperature Protection (OTP) and internal slope
compensation. It provides the users a superior AC/DC
power application of higher efficiency, low external
component counts a nd lower cost solution.
To protect the external power MOSFET from being
da maged by supply over voltage, the R7731A output driver
is cla mped at 12V . Furthermore, R7731A features fruitful
protections like Over Load Protection (OLP) and Over
Voltage Protection (OVP) to eliminate the external
protection circuits and provide reliable operation. R7731A
is available in SOT -23-6 and DIP-8 packages.
Burst Triple Mode PWM Flyback Controller
Features
zz
zz
zVery Low Start-up Current (<30μμ
μμ
μA)
zz
zz
z10/14V UVLO
zz
zz
zSoft Start Function
zz
zz
zCurrent Mode Control
zz
zz
zJittering Switching Frequency
zz
zz
zInternal Leading Edge Blanking
zz
zz
zBuilt-in Slope Compensation
zz
zz
zBurst Triple Mode PWM for Green-Mode
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zCycle-by-Cycle Current Limit
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zz
zFeedback Open Protection
zz
zz
zOver Voltage Protection
zz
zz
zOver Temperature Protection
zz
zz
zOver Load Protection
zz
zz
zSoft Driving for Reducing EMI
zz
zz
zDriver Capability ±±
±±
±200mA
zz
zz
zHigh Noise Immunity
zz
zz
zOpto-Coupler Short Protection
zz
zz
zRoHS Compliant and Halogen Free
Applications
zAda ptor and Battery Charger
zA TX Standby Power
zSet-Top Box (STB)
zD VD and CD(R)
zTV/Monitor Standby Power
zPC Peripherals
Ordering Information
R7731A Package Type
E : SOT-23-6
N : DIP-8
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
IDP=W IDP= : Product Code
W : Date Code
R7731AGN : Product Number
YMDNN : Date Code
R7731AGE
R7731AGE
RichTek
R7731A
GNYMDNN
R7731A
2R7731A-10 August 2011www.richtek.com
Pin No .
SOT-23-6 DIP8
Pi n Name Pi n Function
1 8 GND Ground.
2 7 COMP
Comparator Input. By connecting an opto-coupler to this pin, the peak
cur rent set point is adjus t ed accor dingly t o the out put pow er requi rement .
3 5 R T Se t the sw it chi ng frequency by connect ing a r esistor to G ND .
4 4 CS Pri mary Current Sense.
5 2 VDD IC Power Supply.
6 1 GATE Gate D ri ver Out put to dr ive t he exte rn al M OS FET.
-- 3, 6 NC
No Internal Connection.
Functional Pin Description
Pin Configurations (TOP VIEW)
SOT-23-6 DIP-8
Typical Application Circuit
GND COMP RT
GATE VDD CS
4
23
56
678
4
5
23
GATE VDD NC CS
RTNCCOMPGND
VO+
RT
COMP
GND
VDD
GATE
CS
R7731A
AC Mains
(90V to 265V)
VO-
*
* : See Application Information
R7731A
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R7731A-10 August 2011 www.richtek.com
Function Block Diagram
LEB
VDD
R
SQ
OTP
SS
X3
Slope
Ramp
Burst
Triple Mode
COMP
VBURL
VBURH
VDD
PWM
comparator
Counter
Shutdown
Logic
COMP open
sensing
Brown out
sensing
Dmax
Jittering Oscillator
POR
27V
Bias &
Bandgap
UVLO
OVP
RT
GATE
GND
CS
COMP
14V/10V
OLP
Constant
Power
Soft
Driver
+
-
+
-
+
-
-
R7731A
4R7731A-10 August 2011www.richtek.com
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
VDD Se ction
VDD O v er Volt age P rotection Level V OVP 25.5 27 28.5 V
O n Thr eshold V olt age V TH_ON 13 14 15 V
VDD On/Off Hyste resis VDD_HYS 3 4 5 V
St ar t-up Current IDD_ST V
DD = V TH_ON0.1V -- 20 30 μA
O p er ating Cur rent I DD_OP VDD = 15 V , RT = 1 00kΩ,
GATE = Open, VCOMP = 2. 5V -- 1.1 2.2 mA
V DD Hol dup M ode Hyster es is
E nding Level VDD_HYS V
COMP < 1.6 V - - 11.5 -- V
V DD Hol dup M ode Entry Level V DD_LOW V
COMP < 1.6 V - - 11 -- V
VDD Cl am p Voltage V DD_CLAMP -- 29 -- V
O scil lator Secti on ( RT pi n)
N or mal PWM F requency f OSC R
T = 100kΩ 60 65 70 kHz
To be continued
Recommended Operating Conditions (Note 4)
zSupply Input Voltage, VDD ------------------------------------------------------------------------------------------------- 12V to 25V
zOperating Frequency ------------------------------------------------------------------------------------------------------- 50k to 130kHz
zJunction T emperature Range---------------------------------------------------------------------------------------------- 40°C to 125°C
zAmbient T emperature Range---------------------------------------------------------------------------------------------- 40°C to 85°C
Absolute Maximum Ratings (Note 1)
zSupply Input Voltage, VDD ------------------------------------------------------------------------------------------------- 0.3V to 30V
zGATE Pin---------------------------------------------------------------------------------------------------------------------- 0.3V to 20V
zRT, COMP, CS Pin ---------------------------------------------------------------------------------------------------------- 0.3V to 6.5V
zIDD ------------------------------------------------------------------------------------------------------------------------------- 10mA
zPower Dissipation, PD @ TA = 25°C
SOT-23-6 ---------------------------------------------------------------------------------------------------------------------- 0.4W
DIP-8 --------------------------------------------------------------------------------------------------------------------------- 0.714W
zPa ckage Thermal Re sistance (Note 2)
SOT-23-6, θJA ----------------------------------------------------------------------------------------------------------------- 250°C/W
DIP-8, θJA ---------------------------------------------------------------------------------------------------------------------- 140°C/W
zJunction T emperature------------------------------------------------------------------------------------------------------- 150°C
zLead T emperature (Soldering, 10 sec.)--------------------------------------------------------------------------------- 260°C
zStorage T emperature Range ---------------------------------------------------------------------------------------------- 65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 4kV
MM (Ma chine Mode) -------------------------------------------------------------------------------------------------------- 250V
(VDD = 15V, VDD bypass capacitor=0.1μF, RT = 100kΩ, TA = 25°C, unless otherwise specified)
R7731A
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R7731A-10 August 2011 www.richtek.com
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Parameter Symbol Test Conditions Min Typ Max Unit
Fr equency Jit tering Range -- ±6 -- %
PWM Frequency Jit ter Period TJIT Fo r 65 kHz -- 4 -- ms
Maximum Dut y Cycle D MAX 70 75 80 %
Fr equency Variat ion Ve rsus VDD
Deviation fDV V
DD = 12V to 25V - - - - 2 %
Fr equency Variat ion Ve rsus
Tempe ra ture Deviati on fDT T
A = 30°C to 105°C (No t e 5) -- -- 5 %
C OMP Input Secti on
Open Loop Volt age VCOMP_OP COMP pin open 5.2 5.6 6 V
C O MP Op en- loop P r otecti on Del ay
Cycles TOLP R
T = 100kΩ -- 60 -- ms
Short Circuit Current I ZERO V
COMP = 0V -- 1.2 2.2 mA
Curren t-Se nse Section
In it ia l P eak Cu rre n t Li mit Offse t V CSTH 0.8 0.85 0.9 V
Leadi ng Edg e B lanking Ti m e TLEB -- 420 520 ns
P r opagati on De lay Ti me TPD -- 100 -- ns
GATE Secti on
R isi ng Ti me TR V
DD = 15V , CL = 1nF - - 250 350 ns
Falling Tim e TF V
DD = 15V , CL = 1n F -- 150 25 0 ns
G at e Ou tput Cl am ping Vol tage VCLAMP V
DD = 22V -- 1 2 -- V
O ver Tem per at ur e Pr ot ect ion TOTP 140 -- -- °C
OTP Hysteresis TOTP_HYS -- 30 -- °C
R7731A
6R7731A-10 August 2011www.richtek.com
DMAX vs. Temperature
70
71
72
73
74
75
76
77
78
79
80
-40-200 20406080100120
Tempera tu re (°C )
DMAX (%)
Typical Operating Characteristics
VTH vs . Te m perature
9
10
11
12
13
14
15
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temper ature (°C)
VDD (V)
VTH_ON
VTH_OFF
IDD_ST vs. Temperature
10
12
14
16
18
20
22
24
26
28
-40 -15 10 35 60 85 110 135
Temperat ur e (°C)
IDD_ST (µA)
VDD = 13V
IDD_OP vs. Temperature
1.25
1.30
1.35
1.40
1.45
1.50
1.55
-40 -15 10 35 60 85 110 135
Tempera tu re (°C )
IDD_OP (mA)
VCOMP = 2V, C L = 1nF
VDD = 11V
VDD = 27V VDD = 15V
fOSC vs. Temperature
57
58
59
60
61
62
63
-40 -15 10 35 60 85 110 135
Tempera tu re (°C)
fOSC (kHz)
VDD = 11V
VDD = 27V
VDD = 15V
VCOMP vs. Temperature
5.40
5.44
5.48
5.52
5.56
5.60
-40 -20 0 20 40 60 80 100 120
Temperatur e (°C)
VCOMP
COMP Open Voltage
R7731A
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R7731A-10 August 2011 www.richtek.com
VCLAMP vs. VDD
7
8
9
10
11
12
13
11 12 13 14 15 16 17 18 19 20 21 22
VDD (V)
VCLAMP (V)
ISOURCE = 20mA
VGATE_OFF vs. VDD
400
425
450
475
500
525
550
575
600
11 12 13 14 15 16 17 18 19 20 21 22
VDD (V)
VGATE_OFF (mV)
ISINK = 20mA
ISUPPLY vs. Temperature
0.30
0.35
0.40
0.45
0.50
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
ISUPPLY (mA)
COMP Pin Open
No Gate Output
ISUPPLY = IDD_OP ICOMP
ISUPPLY vs. VDD
0.408
0.410
0.412
0.414
0.416
0.418
0.420
0.422
0.424
0.426
11 12 13 14 15 16 17 18 19 20 21 22
VDD (V)
ISUPPLY (mA)
COMP Pin Open
No Gate Output
ISUPPLY = IDD_OP ICOMP
VCLAMP vs. Tem perature
10.0
10.5
11.0
11.5
12.0
12.5
13.0
-40 -15 10 35 60 85 110 135
TemperatureC)
VCLAMP (V)
VDD = 20V, CL = 1nF
GATE vs. Te m pe rature
0
50
100
150
200
250
300
350
-40 -25 -10 5 20 35 50 65 80 95 110 125
Tempera tu re (°C )
GATE (ns)
VDD = 20V, CL = 1nF
Rising
Falling
R7731A
8R7731A-10 August 2011www.richtek.com
VCSTH vs. Temperature
0.800
0.815
0.830
0.845
0.860
0.875
0.890
-40 -25 -10 5 20 35 50 65 80 95 110 125
TemperatureC)
VCSTH (V)
R7731A
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R7731A-10 August 2011 www.richtek.com
Application Information
UVLO
Under Voltage LockOut (UVLO) block is to ensure VDD
has reached proper operation voltage before we enable
the whole IC blocks. To provide better temperature
coefficient and precise UVLO threshold voltage, the
reference voltage of hysteresis voltage (10V / 14V) is from
band-ga p block directly . By this way, R7731A can operate
more reliable in different environments.
The maximum start-up current (30μA) is only for lea kage
current of IC at UVLO(on)-0.1V . The external al-ca pacitor
on VDD may have 5 to 6μA extra leakage current. So
designed start-up current of the system should exceed
36μA or more and IC can start up normally. In addition,
designed start-up current of system should be le ss than
380μA, a nd IC can work normally at hiccup mode.
Jittering Oscillator
For better EMI performance, R7731A will operate the
system with ±6% frequency deviation around setting
frequency.
To guarantee precise frequency, it is trimmed to 5%
tolerance. It also generates slope compensation saw-tooth,
75% maximum duty cycle pulse a nd overloa d protection
slope. By adjusting resistor of RT pin according to the
following formula :
Figure 1. Competitor
VCS VOUT
VCS
(500mV/Div)
VOUT
(2V/Div)
)(kR
6500
(kHz)f T
OSC
Ω
=
It ca n typically operate between 50kHz to 130kHz. Note
that RT pin can't be short or open otherwise oscillator will
not operate.
Built-in Slope Compensation
To reduce component counts, slope compensation is
implemented by internal built-in saw-tooth. Since it's built-
in, it's compromised between loop gain and sub-harmonic
reduction. In general design, it ca n ca ncel sub-harmonic
to 90Vac.
Leading Edge Blanking (LEB)
MOSFET COSS, secondary rectifier reverse recovery
current and gate driver sourcing current comprise initial
current spike. The spike will seriously disturb current mode
operation especially at light load and high line. R7731A
provides built-in 420ns LEB to guarantee proper operation
in diverse design.
Noise Immunity
Current mode controller is very sensitive to noise. R7731A
ta kes the adva ntages of Richtek long term experience in
designing high noise immunity current mode circuit and
layout. Also, we a mplify current sense signal to compare
with feedba ck signal instea d of dividing feedba ck signal.
All the effort is to provide clean and reliable current mode
operation.
Soft-Start
During initial power on, especially at high line, current
spike is kind of unlimited by current limit. Therefore,
besides cycle-by-cycle current limiting, R7731A still
provides soft-start function. It effectively suppresses the
start-up current spike. As shown in the Figure 1 and
Figure 2, the start-up VCS is about 0.3V lower than
competitor. The typical soft-start duration is 4ms (RT =
100kΩ). Again, this will provide more reliable operation
and possibility to use smaller current rating power
MOSFET.
R7731A
10 R7731A-10 August 2011www.richtek.com
Gate Driver
A totem pole gate driver is fine tuned to meet both EMI
and efficiency requirement in low power application. An
internal pull low circuit is a ctivated after pretty low VDD to
prevent external MOSFET from accidentally turning on
during UVLO.
Burst Triple Mode
To fulfill green mode requirement, there are 3 operation
modes in R7731A. Plea se also refer to Figure 3 for details.
``
``
`PWM Mode
For most of load condition, the circuit will run at traditional
PWM current mode.
``
``
`Burst Mode
During light load, switching loss will dominate the power
efficiency calculation. This mode is to cut switching
loss. As shown in Figure 3, when the output load gets
light, feedback signal drops and touches VBURL (Typical
value is 1.75V). Clock signal will be blanked and system
ceases to switching. After VOUT drops and feedback
signal goes back to VBURH (1.8V, typically), switching
will be resumed. Burst mode so far is widely used in
low power a pplication because it's si mple, relia ble a nd
will not have a ny patent infringement issue.
``
``
`VDD Holdup Mode
When the VDD drops down to VDD turn off threshold
voltage, the system will be shut down. During shut down
period, controller does nothing to a ny load change and
might cause VOUT down. To avoid this, when VDD drops
to a setting threshold, 11V, the hysteresis comparator
will bypass PWM and burst mode loop and force
switching at a very low level to supply energy to VDD
pin. The designed value is 1 1.25V with 0.5V hysteresis
band.
Furthermore, VDD holdup mode is only designed to
prevent VDD from touching turn off threshold voltage under
light load or load transient moment. Relative to burst
mode, switching loss will increase on the system at
VDD holdup mode, so it is highly recommended that
the system should avoid operating at this mode during
light load or no loa d condition, normally.
Figure 3. Burst Triple Mode
Figure 2. R7731A
VCS VOUT
VCS
(500mV/Div)
VOUT
(2V/Div)
Load
VDD
Light
Load
Normal
Operation No Load
VCOMP
VGATE
VBURH
VBURL
(VDD Holdup Mode)
VDD_High
VDD_Low
R7731A
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R7731A-10 August 2011 www.richtek.com
Protection
R7731A provides fruitful protection functions that intend
to protect system from being da maged. All the protection
functions can be listed a s below :
``
``
`Cycle-by-Cycle Current Limit
This is a basic but very useful function and it can be
implemented easily in current mode controller .
``
``
`Over Load Protection
Long time cycle-by-cycle current limit will lead to system
thermal stress. To further protect system, system will
be shut down after about 4096 clock cycles. it's about
60ms delay in 67kHz operation. After shutdown, system
will resume and behave as hiccup. By proper start-up
resistor design, thermal will be averaged to an
a cceptable level over the ON/OFF cycle of IC. This will
last until fault is removed. #It's highly re commended to
add a resistor in parallel with the opto-coupler . To provide
sufficient bia s current to make TL-431 regulate properly ,
1.2kΩ resistor is suggested.
``
``
`Brownout Protection
During heavy load, this will trigger 60ms protection and
shut down the system. If it's in light load condition,
system will be shut down after VDD is running low and
triggers UVLO.
``
``
` OVP
Output voltage can be roughly sensed by V DD pin.If the
sensed voltage reaches 27V threshold, system will be
shut down after 20μs deglitch delay.
``
``
`Feedback Open and Opto-Coupler Short
This will trigger OVP or 60ms delay protection. It
depends on which one occurs first.
``
``
`OTP
Internal OTP function will protect the controller itself
from suffering thermal stress and permanent da mage. It
stops the system from switching until the temperature
is under threshold level. Meanwhile, if VDD reaches VDD
turn off threshold voltage, system will hiccup till over
temperature condition is gone.
Figure 4. R-C Filter on CS Pin
Negative Voltage Spike on Each Pin
Negative voltage (< 0.3V) on each pin will cause substrate
injection. It leads to controller damage or circuit false
trigger. Generally, it happens at CS pin due to negative
spike because of improper layout or inductive current
sense resistor. Therefore, it is highly recommended to
add a R-C filter to avoid CS pin damage, as shown in
Figure 4. Proper layout a nd careful circuit design should
be done to guara ntee yield rate in ma ss production.
VDD
GATE
CS
R7731A
AC Mains
(90V to 265V)
R-C Filter
R7731A
12 R7731A-10 August 2011www.richtek.com
Auxiliary
Ground (c)
IC
Ground (d)
Trace Trace Trace
MOSFET
Ground (b)
CBULK Ground (a)
RT
COMP
GND
GATE
CS
R7731A
AC Mains
(90V to 265V)
VDD
CBULK (a)
(d) (b)
(1)
(c)
(2)
+
Figure 5. PCB Layout Guide
Layout Consideration
A proper PCB layout can abate unknown noise interference
and EMI issue in the switching power supply . Plea se refer
to the guidelines when you want to design PCB layout for
switching power supply:
The current path (1) from bulk capacitor, transformer,
MOSFET, Rcs return to bulk capacitor is a huge high
frequency current loop. It must be a s short a s possible to
decrease noise coupling and kept a space to other low
voltage traces, such a s IC control circuit paths, especially .
Besides, the path (2) from RCD snubber circuit to
MOSFET is also a high switching loop, too. So keep it a s
small as possible.
It is good for reducing noise, output ri pple and EMI issue
to separate ground traces of bulk ca pacitor (a), MOSFET
(b), auxiliary winding (c) a nd IC control circuit (d). Finally ,
connect them together on bulk ca p acitor ground (a). The
areas of these ground tra ces should be kept large.
Placing bypa ss ca pacitor for abating noise on IC is highly
recommended. The bypa ss ca pacitor should be pla ced as
close to controller as possible.
To minimize reflected tra ce inductance and EMI minimize
the area of the loop connecting the secondary winding,
the output diode, and the output filter ca pacitor. In addition,
provide suff icient copper area at the a node a nd cathode
terminal of the diode for heatsinking. Provide a larger area
at the quiet cathode terminal. A large anode area can
increa se high-frequency radiated EMI.
R7731A
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R7731A-10 August 2011 www.richtek.com
Outline Dimension
AA1
e
b
B
D
C
H
L
SOT-23-6 Surface Mount Package
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.889 1.295 0.031 0.051
A1 0.000 0.152 0.000 0.006
B 1.397 1.803 0.055 0.071
b 0.250 0.560 0.010 0.022
C 2.591 2.997 0.102 0.118
D 2.692 3.099 0.106 0.122
e 0.838 1.041 0.033 0.041
H 0.080 0.254 0.003 0.010
L 0.300 0.610 0.012 0.024
R7731A
14 R7731A-10 August 2011
www.richtek.com
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
J
A
B
E
C
I
D
L
F
8-Lead DIP Plastic Package
Dimensions In Millimeters Dimension s In Inches
Symbol Min Max Min Max
A 9.068 9.627 0.357 0.379
B 6.198 6.604 0.244 0.260
C 3.556 4.318 0.140 0.170
D 0.356 0.559 0.014 0.022
E 1.397 1.651 0.055 0.065
F 2.337 2.743 0.092 0.108
I 3.048 3.556 0.120 0.140
J 7.366 8.255 0.290 0.325
L 0.381 0.015