HEWLETT PACKARD GD High CMR Analog Isolation Amplifiers Technical Data Features Fast Propagation Delays for Over-Current and Fault Detection Sensing High Common Mode Rejection (CMR): 30 kV/us at Vom = 1000 V* 3% Gain Tolerance: HCPL-7820 5% Gain Tolerance: HCPL-7825 0.05% Nonlinearity Low Offset Voltage and Off- set Drift vs. Temperature 200 kHz Bandwidth Performance Specified for Common Motor Control Applications over -40C to 100C Temperature Range Worldwide Safety and Regulatory Approval: UL 1577 (3750 V rms/1 Min), VDE 0884 and CSA Compact Auto-Insertable Standard 8-Pin DIP Package Advanced Sigma-Delta (2A) A/D Converter Technology 1 um CMOS IC Technology Applications Motor Phase and Rail Current Sensing General Purpose Current Sensing and Monitoring High-Voltage Monitoring Switched Mode Power Supply Signal Isolation General Purpose Analog Signal Isolation Transducer Isolation Description The HCPL-7820/7825 high CMR isolation amplifier consists of a sigma-delta analog-to-digital converter optically coupled to an integrated output digital-to-analog converter. When used with a shunt resistor in the current path, the HCPL-7820/7825 provides a cost-effective, auto-insertion compatible current sense solution. Fast propagation delays allow this part to be used in either motor drive or inverter applications for either phase current monitoring or rail current fault detection applications. High isolation mode HCPL-7820 HCPL-7825 rejection makes this product suitable for noisy electrical environments, such as those generated by the high switching rates of power IGBTs. Low offset voltage together with low offset change vs. temperature permits accurate use of auto-calibration techniques. Tight gain tolerance with good nonlinearity further provide the characteristics needed to insure highly accurate motor speed control. A high operating temperature range with specified performance parameters allow Functional Diagram , /pp1 Ipp2 5 V; _ ~ sv DD1 Db2 2 Vins o 3 ViIN- OJ GND1 CMR SHIELD A 0.1 uF bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. *The terms common-mode rejection (CMR) and isolation-mode rejection (IMR) are used interchangeably throughout this data sheet. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 5965-3591E 1-233this device to be used in hostile industrial environments. This performance is delivered in an auto-insertable, industry standard Ordering Information HCPL-782x. Option yyy 3% Gain Tolerance 5% Gain Tolerance 8-pin DIP package that meets major worldwide regulatory and safety approval ratings to help ensure that your equipment can be certified in many geographic areas. 300 = Gull Wing Surface Mount Lead Option 500 = Tape/Reel Package Option (1 k min.) Option datasheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information. Package Outline Drawings Standard DIP Package 9.40 (0.370) 9.90 (0.390) [a (7) (6) 5) - | HP 7820 YYWW PIN ONE rp (2) (3) Y) |_ TYPE NUMBER DATE CODE 1-234 1.19 (0.047) MAX. _. L = = 78 (0.070) MAX. 4,70 (0.185) MAX. PIN ONE |! t Fost (0.020) MIN. 2.92 (0.115) MIN. 0.76 (0.030) ~ )_-| _ 0.65 (0.025) MAX. 1.24 (0.049) "| [*_ 2.28 (0.090) 2:80 (0.110) DIMENSIONS IN MILLIMETERS AND (INCHES). ee 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310) 0.20 (0.008) 0.33 (0.013) | 5 TYP. k PIN DIAGRAM Vpp1 Vpp2 Vins Vout+ {7 Vin- VYout- GND1 GND2 *] fe) fe) ie] le] le} SY lelGull Wing Surface Mount Option 300* PIN LOCATION (FOR REFERENCE ONLY) 1.02 (0.040) . | ~~ 719 (0.047) C]) CJ Cd oO 6.350 + 0.25 (0.250 + 0.010) 9.65 + 0.25 \ (0.380 + 0.010) MOLDED OOCICO Oo +| i 0.380 (0.015) 1.19 (0.047) 0.635 (0.025) 1.78 (0.070) 1.780 9.65 + 0.25 , (0.070) (0.380 + 0.010) 119, . (0.047) MAX 7.62 + 0.25 MAX. (0.300 + 0.010) 4.19 wax T (0.013) os 1.080 + 0.320 t 0.635 + 0.25 4 (0.043 + 0.013) ) [* (0.025 + 0.010) 0.51 +0.130 . 2.5404 (0.020 + 0.005) rat 12 NOM. (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 LEAD COPLANARITY *Refer to Option 300 Data Sheet for more information. Maximum Solder Reflow Thermal Profile TEMPERATURE - C 260 240 220 200 180 160 140 120 100 80 60 40 20 0 AT=11 0.3C/SEC T = 100C, 1.5C/SEC 0 1 2 3 4 5 6 7 8 9 TIME MINUTES XX.XXX = 0.005 MAXIMUM: 0.102 (0.004) 10 11 12 (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.) 1-235Regulatory Information The HCPL-7820/7825 has been approved by the following organizations: UL CSA VDE Recognized under UL 1577, Approved under CSA Component Approved according to VDE Component Recognition Program, Acceptance Notice #5, File CA 0884/06.92. FILE 55361. 88324. Insulation and Safety Related Specifications Parameter Symbol | Value | Units Conditions Min. External Air Gap Ld01) 7.4 mm Measured from input terminals to output (External Clearance) terminals, shortest distance through air Min. External Tracking Path | LdO2) 8.0 mm Measured from input terminals to output (External Creepage) terminals, shortest distance path along body Min. Internal Plastic Gap 0.5 mm Through insulation distance, conductor to (Internal Clearance) conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity Tracking Resistance CTI 175 V DIN IEC 112/VDE 0308 Part 1 (Comparative Tracking Index) Isolation Group Ila Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 surface mount classification is Class A in accordance with CECC 00802. VDE 0884 (06.92) Insulation Characteristics Description Symbol Characteristic Unit Installation classification per DIN VDE 0110, Table 1 for rated mains voltage < 300 V rms LIV for rated mains voltage < 600 V rms I-III Climatic Classification 40/100/21 Pollution Degree (DIN VDE 0110, Table 1)* 2 Maximum Working Insulation Voltage Viorm 848 V peak Input to Output Test Voltage, Method b** Ver 1591 V peak Ver = 1.875 x Viorw, Production test with t, = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a** Ver 1273 V peak Vpr = 1.5 x Viorm, Type and sample test with t, = 60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage** Vir 6000 V peak (Transient Overvoltage tpp = 10 sec) Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure 22) Case Temperature Ts 175 C Input Power Ps input 80 mW Output Power Ps ontput 250 mW Insulation Resistance at Ts, Vij = 500 V Rg > 1x10" Q *This part may also be used in Pollution Degree 3 environments where the rated mains voltage is < 300 V rms (per DIN VDE 0110). **Refer to the front of the optocoupler section of the current catalog for a more detailed description of VDE 0884 and other product safety requirements. Note: Optocouplers providing safe electrical separation per VDE 0884 do so only within the safety-limiting values to which they are qualified. Protective cut-out switches must be used to ensure that the safety limits are not exceeded. 1-236Absolute Maximum Ratings Parameter Symbol Min, Max. Unit Note Storage Temperature Ts -55 125 C Ambient Operating Temperature Th -40 100 C Supply Voltages Vopi, Vop2 0.0 5.5 Vv Steady-State Input Voltage Vins, Vin. -2.0 Vpn1 +9.5 Vv Two Second Transient Input Voltage -6.0 Output Voltages Vour+;, Vout. -0.5 Vpp2 +9.5 Vv Lead Solder Temperature Tis 260 C 1 (1.6 mm below seating plane, 10 sec.) Reflow Temperature Profile See Package Outline Drawings Section Recommended Operating Conditions Parameter Symbol Min Max. Unit Note Ambient Operating Temperature Ty -40 100 C Supply Voltages Vapi Vope 4.5 5.5 V Input Voltage Ving> Vin. -200 200 mV 2 1-237DC Electrical Specifications All specifications are at the nominal (typical) operating conditions of Viyi = 0 V, Viv. = 0 V, Ta = 25C, Vopi = 5 V and Vppe = 5 V, unless otherwise noted. Current Parameter Symbol | Min. | Typ. |Max.| Unit Test Conditions Fig. | Note Input Offset Voltage Vos -0.8 0.45 | 1.7 mV 1 3 -2.0 0.45 | 2.9 -40C < Ty < 100C 1,2,3 4.5 V < (Vpn, Vope) $ 5.5 V Absolute Value of Input | AVos/AT | 7.8 pv/C 12 | 3,4 Offset Change vs. Temperature Gain: HCPL-7820 G 7.76 | 8.00 | 8.24] V/V | -200mV< Vin4 < 200 mV 5 7.60 | 8.00 | 8.40 -200 mV < Vivi < 200 mV 5,6,7 -40C < Ty < 100C 4.5 V< (Vpp1, Vong) $ 5.5 V Gain: HCPL-7825 G 7.60 | 8.00 | 8.40] V/V | -200mV< Vin4 < 200 mV 5 744 | 8.00 | 8.56 -200 mV < Vivi < 200 mV 5,6,7 -40C < Ty < 100C 4.5 V< (Vpp1, Vong) $ 5.5 V 200 mV Nonlinearity NL200 0.06 | 0.15 % -200 mV < Ving S$ 200 mV 5,8 5 0.3 -200 mV < Viyi < 200 mV 5,8, -40 < Ty < 100C 9,10, 4.5 V< (Vpp1, Vong) $ 5.5 V 12 100 mV Nonlinearity NLj00 0.03 | 0.08 -100 mV < Vin4 < 100 mV 5,8 0.1 -100 mV < Vivi < 100 mV 5,8, -40C < Ty < 100C 9,11, 4.5 V< (Vpp1, Vong) $ 5.5 V 12 Maximum Input Voltage | Vine | nax 320 mV 4 Before Output Clipping Average Input Bias li -1 pA 13 6 Current Average Input Resistance Rw 280 kQ Input DC Common-Mode CMRRw 52 dB Rejection Ratio Output Resistance Ro 1.2 Q Output Low Voltage Vou 1.30 Vv Vin+ = 400 mV 4 7 Output High Voltage Vou 3.90 Vv Ving = -400 mV Output Common- Vocm 2.30 2.60 | 2.90 Vv -400 mV < Vy, < 400 mV Mode Voltage -40C < Ty < 100C Input Supply Current Ippi 11.1 117.0] mA | 4.5 VS (pp1, Vppa) < 5.5 V 14 Output Supply Current Ipp2 10.0 | 14.0 | mA 15 Output Short-Circuit Hose! 12 mA | Voor = 0 Vor Vopp 8 1-238AC Electrical Specifications All specifications and figures are at the nominal (typical) operating conditions of Vy, = 0 V, Vix. = 0 V, Ty = 25C, Vpp; = 5 V and Vppe = 5 V, unless otherwise noted. Parameter Symbol | Min. | Typ.| Max.| Unit Test Conditions Fig. | Note Isolation Mode Rejection IMR 20 30 kV/jus | Vy, = 1 kV 16 9 -40C < Ty < 100C 4.5 V< (Vpn, Vop2) S$ 5.5 V Isolation Mode Rejection | IMRR >140 dB 10 Ratio at 60 Hz Propagation Delay to 50%| tppsy | 1.20 | 1.85] 2.85 Us Vine = 0 to 100 mV step 17,18 Propagation Delay to 90% | tppoo | 1.60 | 2.75 | 4.10 -40 < Ty < 100C Rise/Fall Time (10-90%) | typ [0.85 | 1.50] 2.25 4.5 VS (Vppi, Vopa) $ 5.5 V Small-Signal Bandwidth fsqp 150 | 200 | 380] kHz | -40 < Th < 100C 17,19, (-3 dB) 4.5V< (Vpp1, Vop2) S$ 5.5V | 20 Small-Signal Bandwidth fage 85 (-45) RMS Input-Referred Noise Vy 1.4 mVrms | In recommended 21,24] 11 application circuit Power Supply Rejection PSR 150 mV p-p 12 Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of Viv. = 0 V, Vix. = 0 V, Ty = 25C, Vpp; = 5 V and Vppe = 5 V, unless otherwise noted. Parameter Symbol | Min. | Typ. | Max.| Unit Test Conditions Fig. | Note Input-Output Momentary} Vigg |3750 Vrms | t = 1 min., RH < 50% 13,14 Withstand Voltage* Input-Output Rro_ =|: 10!2 | 1018 Q Tr = 25C | Vio = 500 Vde 13 Resistance 1011 T = 100C Input-Output Cro 0.7 pF f= 1 MHz Capacitance Input IC Junction-to- Bie4 96 C/W | Thermocouple located at Case Thermal center underside of Resistance package Output IC Junction-to- Bin0 114 C/W Case Thermal Resistance *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification, or HP Application Note 1074, Optocoupler Input-Output Endurance Voltage. 1-239Notes: 1. 2 HP recommends the use of non- chlorine activated fluxes. . If Vix. is brought above Vpp,-2 V with respect to GND 1 an internal test mode may be activated. This test mode is not intended for customer use. . Exact offset value is dependent on layout of external bypass capacitors. The offset value in the data sheet corresponds to HPs recommended layout (see Figures 26 and 27). . Data sheet value is the average magnitude of the difference in offset voltage from T, = 25C to Ty = 100C, expressed in microvolts per C. . Nonlinearity is defined as half of the peak-to-peak deviation from the best- fit gain line, expressed as a percentage of the full-scale differential output voltage. . Because of the switched-capacitor nature of the input sigma-delta A/D converter, time-averaged values are shown. 7. When the differential input signal exceeds approximately 320 mV, the outputs will limit at the typical values shown. 1-240 8. 10. 11. Short-circuit current is the amount of output current generated when either output is shorted to Vpp or ground. . IMR (also known as CMR or Common Mode Rejection) specifies the mini- mum rate of rise of an isolation mode noise signal at which small output perturbations begin to appear. These output perturbations can occur with both the rising and falling edges of the isolation mode waveform and may be of either polarity. A CMR failure is defined as a perturbation exceeding 200 mV at the output of the recom- mended application circuit (Figure 24). See applications section for more information on CMR. IMRR is defined as the ratio of differential signal gain (signal applied differentially between pins 2 and 3) to the isolation mode gain (input pins tied to pin 4 and the signal applied between the input and the output of the isolation amplifier) at 60 Hz, expressed in dB. Output noise comes from two primary sources: chopper noise and sigma- delta quantization noise. Chopper noise results from chopper stabiliza- tion of the output op-amps. It occurs at 12. 13. 14. a specific frequency (typically 500 kHz) and is not attenuated by the on-chip output filter. The on-chip filter does eliminate most, but not all, of the sigma-delta quantization noise. An external filter circuit may be easily added to the external post-amplifier to reduce the total RMS output noise. See applications section for more information. Data sheet value is the amplitude of the transient at the differential output of the HCPL-7820/7825 when a 1 V,.p, 1 MHz square wave with 200 ns rise and fall times (measured at pins 1 and 8) is applied to both Vpp; and Vppp. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together. In accordance with UL 1577, for devices with minimum Vigo specified at 3750 V rms, each optocoupler is proof-tested by applying an insulation test voltage greater than 4500 V rms for one second (leakage current detection limit I, < 5 WA). This test is performed before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table.Vpp1 Vpp2 +15V - 0.1 pF & 4 Lu it, 8 I o = 0.1 pF _L 2 7 = 2 7 10K o AWW IN HT on tur HCPL-7820/7825 Vout He vay 3 6 KO Hf Ape24cp Pe om GAIN = 100 2 = 4 5 0.47 0.47 | 1 HF i HF = HF ry s as < "40-200 20 40 60 80 100 = = 15V Ta TEMPERATURE C Figure 1. Input Offset Voltage Test Circuit. Figure 2. Input Offset Change vs. Temperature. > 4.0 oe & vs. Vpp1 (Vpp2 =5 \ / > w _ _ 3.5 g vs. Vop2 (Vpp1 = V) a NEGATIVE /_ POSITIVE z O OUTPUT 7 | OUTPUT 3 Tp = 25C F 3 7 bi g ( f 5 7 Q. Vpp1=5V | ff E E 99|Vpp1= 2 3 Vpp2=5 vi N\ $ 1 Ta = 25C/ \ 7 9 15 + I 2 > -=/ VW > 1.0 4 06 -04 -02 0 O02 04 06 44 46 48 50 52 54 5.6 Vpp SUPPLY VOLTAGE - V Figure 3. Input Offset Change vs. Vpp, Vin INPUT VOLTAGE - V Figure 4. Output Voltages vs. Input and Vpp2: Voltage. Vpp1 Vpp2 +15V 0.1 pF I. 8 l 0.1 pF == = 0.1 pF _L 404 2 7 10K vi N WW AWW 2 HCPL-7820/7825 Vout 13.2 3 6 joK AD624CD vy GAIN = 10 0.01 pF == 4 5 0.47 0.1 pF " rl a 15V - Figure 5. Gain and Nonlinearity Test Circuit. 1-2410.5 0.4 0.3 0.2 0.1 AG GAIN CHANGE - % -0.2 -0.3 40 -20 0 20 40 60 80 100 Ta TEMPERATURE - C Figure 6. Gain Change vs. Temperature. 0.16 === 200 mV NL 3 0.14) 100 mv NL| / et 1 0.12 7 > S ee E 0.10 7 < wi / z 0.08 A, 3 7 Nppi=5V 3 0.06 yoo? Py IN- = | 0.04 a = a Zz ae 0.02 0 40 -20 0 20 40 60 80 100 Ta TEMPERATURE - C Figure 9. Nonlinearity vs. Temperature. 0.50 - == T, = 100C Tp = 25C > s10=T, = -40C z yore 0.10 2 < Ah 4 = ie a > ia Z 0.05 <u Y z oopersettnseets I wererfs>*" 2 Vpp1=5V Vpp2=5V 01 0 +0.05 +0.10 40.15 +0.20 +0.25 +0.30 FS FULL-SCALE VALUE - V Figure 12. Nonlinearity vs. Full-Scale Value. 1-242 0.3 0.04 a oN 0.2 Ww 0.02 oa x a ON T 0.1} ee = S 4 (? \ Ww vee, Lot a f go 7 3 SV \ a 2 -0.02 t =x wu ~~ oO -0.1 Y WL \ : / 5.04| _[ 200 mv ERROR] < -0.2 x == 100 mV ERROR \ Ta = 25C 0:3 f -0.06)Vpp1 =5V < 0A == vs. Vpp1 (Vpp2 = 5 V) fo 0.08 | __ Woo2= Sy == VS. Vpp2 (Vpp1 = 5 V) uw The 25C 05 Lj 0.10 44 46 48 5.0 52 54 56 -0.2 -0.1 0 0.1 0.2 Vpp SUPPLY VOLTAGE - V Ving INPUT VOLTAGE V Figure 7. Gain Change vs. Vpp; and Figure 8. Nonlinearity Error Plot vs. Vppe2: Input Voltage. 0.080 0.040 vs. Vpp1 (Vpp2 = 5 V) 0.038 vs. Vpp1 (Vpp2 = V) se 0075) 5 == vs. Vpp2 (Vpp1 = 5 VF] eo = vs. V =5 \ | 0.036 on E 0.070 S E 0.034 c = \ Ta = 25C = W 0.065 <A 3 WW 9.032 5 \ 5 5 of 5 9.030 0.060 g | | 9,028 Z 0.055 = 1006 0.050 0.024 44 46 48 50 52 54 56 44 46 48 50 52 54 5.6 Vpp SUPPLY VOLTAGE - V Vpp SUPPLY VOLTAGE - V Figure 10. 200 mV Nonlinearity vs. Vpp1 and Vppp- Figure 11. 100 mV Nonlinearity vs. Vpp, and Vppz- 2 Pa 14 I == Ta = 100C < 0 E13} Ta = 25C --4 E 2 sree Ta = -40C or" it 12 ros 2 -2 5 7 a / 2 IM genttine ec / o 11 A fs? *eeeee ao > of s* 5 (C4 a J P Vpp1=5V a 10 Ws 5 Vpp2=5V 2 F. 2 6 DD2 __ | oa 4s Vpp1=5V z / VIN- = ad 5 9 ry, fs Vpp2 =5 V I / Ta = 25C 2 7 4G Vin-=0V = -8 7 = Bh~ a = 1 [ -10 a 7 anne -6 -4 -2 0 2 4 6 -0.4 -0.2 0 0.2 0.4 Ving INPUT VOLTAGE V Ving INPUT VOLTAGE V Figure 14. Input Supply Current vs. Input Voltage. Figure 13. Input Current vs. Input Voltage.Ipp2 - OUTPUT SUPPLY CURRENT mA 12 r T == Ta = 100C Vpp1=5V == Ta, = 25C Vpp2 =5V sane Ty = -40C Vin-=0V 11 a os TSA s. Le oo 10 _ of "ah 8 -0.4 -0.2 0 0.2 0.4 Vin4 INPUT VOLTAGE - V Figure 15. Output Supply Current vs. Input Voltage. HCPL-7820/7825 PULSE GEN. J Vim Figure 16. Isolation Mode Rejection Test Circuit. 10K AAA V Vpp1 Vpp2 +15V 0.1 pF 1 8 tH = e 0.1 pF L ot uF | 2K VINO 2 r WW MN HCPL-7820/7825 > 0.01 pF == 3 6 2K ii-{ Mc34ost 4 5 0.1 pF 10K + A = = 15V ~ Figure 17. Propagation Delay, Rise/Fall Time and Bandwidth Test Circuit. RELATIVE AMPLITUDE dB = Ta = 25C 5 10 50 100 500 f FREQUENCY - kHz Figure 19. Amplitude Response vs. Frequency. 260 250 240 230 220 210 200 f (-3 dB) -3 dB BANDWIDTH kHz 190 -40 -20 0 Ta TEMPERATURE - C 20 40 60 80 Figure 20. 3 dB Bandwidth vs. Temperature. +0 VouT 100 Vpp2 +15 V 8 0.1 LF = 0.1 pF ] Ik 7 2K = VVV NY 2K 6 AW if Mc34o81 5 d 0.1 LF me 75 L __ pF T 15V 7 3.0 | oa 25 , DELAY TO 90% a =*+DELAY TO 50% 1 == RISE/FALL TIME w 2.0} Woot ey = = DD2 = ceneneoeespeee I ewan - prem aan 15 to=eert= iF Vin = OV io Ving = 0 TO 100 mV STEP "-40 -20 0 20 40 60 80 100 Ta TEMPERATURE - C Figure 18. Propagation Delays and Rise/Fall Time vs. Temperature. 3.0 2.5 2.0 Vn RMS INPUT-REFERRED NOISE mV I I === Vin, = 200 mV == Vin, = 100 mv Ving =O mV T | Vpp1=5V Vpp2=5V Vin-=0V l__T, =25C a 2 . z . * * 2 7 50 100 500 1000 f FREQUENCY - kHz Figure 21. RMS Input-Referred Noise vs. Recommended Application Circuit Bandwidth. 1-243 -O VouTApplications Information Functional Description Figure 23 shows the primary 300 250 Ps, OUTPUT \ functional blocks of the HCPL- 200 p 7820/7825. In operation, the == Pg, INPUT \ 150 \ sigma-delta modulator converts MAX. OPERATING TEMP. IS 100 C the analog input signal into a high-speed serial bit stream. The time average of this bit stream is directly proportional to the input signal. This stream of digital data is encoded and optically trans- mitted to the detector circuit. The detected signal is decoded and converted back into an analog 100 Pg) - POWER - mw 50 100 Ta TEMPERATURE - C Figure 22. Dependence of Safety- Limiting Values on Temperature. VOLTAGE CLOCK REGULATOR GENERATOR signal, which is filtered to obtain the final output signal. Application Circuit The recommended application circuit is shown in Figure 24. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple three-terminal voltage regulator (U1). The voltage from the cur- rent sensing resistor, or shunt (Rgpnsp), is applied to the input of VOLTAGE REGULATOR ISOLATION BOUNDARY I I ISO-AMP LED DRIVE DETECTOR | DECODER ISO-AMP INPUT nt) ENCODER CIRCUIT )a [ CIRCUIT AND D/A oe Lf FILTER B OUTPUT I Figure 23. HCPL-7820/7825 Block Diagram. FLOATING SUPPLY C5 GATE DRIVE 75 pF | cr Leet r R3 AAA FLOATING Wy SUPPLY 10.0 KQ U1 +5V 78L05 +18 V IN OUT ce | 0.1 LF c1 c2 = = 1} 8! {ca LF LF 0.1 pF = R5 7 AWA, NY 39.2 tes u2 u3 bO Vout NE _3| 6 i-{ Mc34ost MOTOR C TAAA ~ 4 8 i 4 ( ) VVV d RsENSE 0 { F HCPL-7820/7825 10.0 Kol ew -15V HVv- Figure 24. Recommended Application Circuit. 1-244the HCPL-7820/7825 through an RC anti-aliasing filter (R5, C3). And finally, the differential output of the isolation amplifier is con- verted to a ground-referenced single-ended output voltage with a simple differential amplifier circuit (U3 and associated components). Although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. Supplies and Bypassing As mentioned above, an inexpen- sive 78L05 three-terminal regula- tor can be used to reduce the gate-drive power supply voltage to 5 V. To help attenuate high- frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulators input bypass capacitor. As shown in Figure 24, 0.1 uF bypass capacitors (C2, C4) should be located as close as possible to the input and output power supply pins of the HCPL-7820/7825. The bypass capacitors are required because of the high-speed digital nature of the signals inside the isolation amplifier. A 0.01 uF bypass capacitor (C3) is also rec- ommended at the input pin(s) due to the switched-capacitor nature of the input circuit. The input bypass capacitor should be at least 1000 pF to maintain gain accuracy of the isolation amplifier. Inductive coupling between the input power-supply bypass capacitor and the input circuit, which includes the input bypass capacitor and the input leads of the HCPL-7820/7825, can introduce additional DC offset in the circuit. Several steps can be taken to minimize the mutual coupling between the two parts of the circuit, thereby improving the offset performance of the design. Separate the two bypass capaci- tors C2 and C3 as much as possible (even putting them on opposite sides of the PC board), while keeping the total lead lengths, including traces, of each bypass capacitor less than 20 mm. PC board traces should be made as short as possible and placed close together or over ground plane to minimize loop area and pickup of stray magnetic fields. Avoid using sockets, as they will typically increase both loop area and inductance. And finally, using capacitors with small body size and orienting them perpendicular to each other on the PC board can also help. For more information concerning inductive coupling, see the Application Note Designing with Hewlett-Packard Isolation Amplifiers. Shunt Resistor Selection The current-sensing shunt resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt Table 1. Current Shunt Summary induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). The value of the shunt should be chosen as a compromise between minimizing power dissipation by making the shunt resistance smaller and improving circuit accuracy by making it larger and using more of the input range of the HCPL-7820/7825. Hewlett- Packard recommends 4 different shunts which can be used to sense average currents in motor drives up to 35 A and 35 hp. Table 1 shows the maximum current and horsepower range for each of the LVR-series shunts from Dale. Even higher currents can be sensed with lower value shunts available from vendors such as Dale, IRC, and Isotek (Isabellen- huette). When sensing currents large enough to cause significant heating of the shunt, the tempera- ture coefficient of the shunt can introduce nonlinearity due to the amplitude dependent temperature rise of the shunt. Using a heat sink for the shunt or using a shunt with a lower tempco can help minimize this effect. The Application Note Designing with Hewlett-Packard Isolation Amplifiers contains additional information on designing with current shunts. The recommended method for connecting the isolation amplifier to the shunt resistor is shown in Shunt Resistor Shunt Maximum Maximum Maximum Part Number Resistance Power Dissipation RMS Current Horsepower Range LVR-3.05-1% 50 mQ 3W 3A 0.8-3.0 hp LVR-3.02-1% 20 mQ 3W 8A 2.2-8.0 hp LVR-3.01-1% 10 mQ 3W 15A 4.1-15 hp LVR-5.005-1% 5 mQ 5 W B35 A 9.6-35 hp 1-245Figure 24. Pin 2 (Vyy+) is con- nected to the positive terminal of the shunt resistor, while pin 3 (Vyv.) is shorted to pin 4 (GND1), with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. This allows a single pair of wires or PC board traces to connect the isolation amplifier circuit to the shunt resistor. In some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. In this case, better performance may be obtained by connecting pin 3 to the negative terminal of the shunt resistor separately from the power supply return path. When connected this way, both input pins should be bypassed. Whether two or three wires are used, it is recommended that twisted-pair wire or very close PC board traces be used to connect the current shunt to the isolation amplifier circuit to minimize electro- magnetic interference to the sense signal. The 39 Q resistor in series with the input lead forms a low-pass anti-aliasing filter with the input bypass capacitor with a 400 kHz bandwidth. The resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the wires or traces connecting the two. Undamped ringing of the input circuit near the input sampling frequency can alias into cs 75 pF J} i +5 V AW 10.0 KQ +5 V +5 V RAAS 20.0 KQ < I, BI lca 0.1 pF R1 2 7 AAA tT LAA J 10.0 KQ U2 Ro 3 6 AAA 7s V 10.0 KQ Al 5 ce_| 2r4B HCPL-7820/7825 Figure 26. Top Layer of Printed Circuit Board Layout. 1-246 the baseband producing what might appear to be noise at the output of the device. PC Board Layout In addition to affecting offset, the layout of the PC board can also affect the common mode rejection (CMR) performance of the isolation amplifier, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMR performance, the layout of the printed circuit board (PCB) should minimize any stray coupling by maintaining the maximum pos- sible distance between the input and output sides of the circuit and ensuring that any ground plane on the PCB does not pass directly below or extend much wider than the HCPL-7820/7825. Using surface-mount components can help achieve many of the PCB objectives discussed in the pre- ceding paragraphs. An example through-hole PCB layout illustrat- ing some of the more important layout recommendations is shown in Figures 26 and 27. See the Application Note Designing with Hewlett-Packard Isolation Amplifiers for more information on PCB layout considerations. TO Vpp1 _j e Gas TO Vop2 TO Rsense, =D @u@=e TO Reense- =D Gms Vout. Gus Qawes Vout o oe Figure 27. Bottom Layer of Printed Circuit Board Layout.Post-Amplifier Circuit The recommended application circuit (Figure 24) includes a post-amplifier circuit that serves three functions: to reference the output signal to the desired level (usually ground), to amplify the signal to appropriate levels, and to help filter output noise. The particular op-amp used in the post-amp is not critical; however, it should have low enough offset and high enough bandwidth and slew rate so that it does not adversely affect circuit performance. The offset of the op- amp should be low relative to the output offset of the HCPL-7820/ 7825, or less than about 5 mV. To maintain overall circuit band- width, the post-amplifier circuit should have a bandwidth at least twice the minimum bandwidth of the isolation amplifier, or about 400 kHz. To obtain a bandwidth of 400 kHz with a gain of 5, the op-amp should have a gain- bandwidth greater than 2 MHz. The post-amplifier circuit includes a pair of capacitors (C5 and C6) that form a single-pole low-pass filter. These capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier (doubling the capacitor values halves the circuit band- width). The component values shown in Figure 24 form a differential amplifier with a gain of 5 and a cutoff frequency of approximately 200 kHz and were chosen as a compromise between low noise and fast response times. The overall recommended application circuit has a band- width of 130 kHz, a rise time of 2.6 us and delay to 90% of 4.2 us. The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure ade- quate CMRR and gain tolerance for the overall circuit. Resistor networks with even better ratio tolerances can be used which offer better performance, as well as reducing the total component count and board space. The post-amplifier circuit can be easily modified to allow for single- supply operation. Figure 25 shows a schematic for a post-amplifier for use in 5 V single-supply appli- cations. One additional resistor is needed and the gain is decreased to allow circuit operation over the full input voltage range. See the Application Note Designing with Hewlett-Packard Isolation Amplifiers for more information on the post-amplifier circuit. Other Information As mentioned above, reducing the bandwidth of the post amplifier circuit reduces the amount of output noise. Figure 21 shows how the output noise changes as a function of the post-amplifier bandwidth. The post-amplifier circuit exhibits a first-order low- pass filter characteristic. For the same filter bandwidth, a higher- order filter can achieve even better attenuation of modulation noise due to the second-order noise shaping of the sigma-delta modulator. For more information on the noise characteristics of the HCPL-7820/7825, see the Application Note Designing with Hewlett-Packard Isolation Amplifiers. The HCPL-7820/7825 can also be used to isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage divider at its input. The only restrictions are that the imped- ance of the divider be relatively small (less than 1 kQ) so that the input resistance (280 kQ) and input bias current (1 WA) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the 39 series damping resistor is not (the resistance of the voltage divider provides the same function). The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. 1-247