1
LTC1061
1061fe
INPUT FREQUENCY GAIN (kHz)
–100
FILTER GAIN (dB)
–80
–60
–40
–20
0
10 20 30 40
1061 TA02
50
2kHz
f
CLK
= 1MHz
0
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
78.7k
4.99k
23.7k
4.99k
165k
5.49k
49.9k
V
–
= –7.5V
165k
4.99k
1k9.31k
165k
V
IN
< 100kHz
7.5V
T
2
CLK IN < 1.2MHz
V
+
= 7.5V
1061 TA01
LTC1061
V
OUT
■
Three Filters in a Single Package
■
Up to 6th Order Filter Functions
■
Center Frequency Range up to 35kHz
■
f
O
× Q Product up to 1MHz
■
Guaranteed
Center Frequency and Q Accuracy Over
Temperature
■
Guaranteed
Low Offset Voltages Over Temperature
■
90dB Signal-to-Noise Ratio
■
Operation from Single 4.7V Supply, Up to ±8V
■
Guaranteed
Filter Specifications with ±5V Supply and
±2.37V Supply
■
Low Power Consumption with Single 5V Supply
■
Clock Inputs T
2
L and CMOS Compatible
■
Available in 20-Pin DIP and 20-Pin SO Wide Package
, LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOSTM
is a trademark of Linear Technology Corporation. All other trademarks are the property of
their respective owners.
TYPICAL APPLICATIO
U
The LTC
®
1061 consists of three high performance, univer-
sal filter building blocks. Each filter building block together
with an external clock and 2 to 5 resistors can produce
various second order functions which are available at its
three output pins. Two out of three always provide low-
pass and bandpass functions while the third output pin
can produce highpass or notch or allpass. The center
frequency of these functions can be tuned with an external
clock or an external clock and a resistor ratio. For Q < 5, the
center frequency ranges from 0.1Hz to 35kHz. For Qs of 10
or above, the center frequency ranges from 0.1Hz to
28kHz.
The LTC1061 can be used with single or dual supplies
ranging from ±2.37V to ±8V (or 4.74V to 16V). When the
filter operates with supplies of ±5V and above, it can
handle input frequencies up to 100kHz.
The LTC1061 is compatible with the LTC1059 single
universal filter and the LTC1060 dual. Higher than 6th
order functions can be obtained by cascading the LTC1061
with the LTC1059 or LTC1060. Any classical filter realiza-
tion can be obtained.
APPLICATIO S
U
DESCRIPTIO
U
FEATURES
High Performance Triple
Universal Filter Building Block
Amplitude Response
■
High Order, Wide Frequency Range Bandpass,
Lowpass, Notch Filters
■
Low Power Consumption, Single 5V Supply,
Clock-Tunable Filters
■
Tracking Filters
■
Antialiasing Filters
6th Order, Clock-Tunable, 0.5dB Ripple Chebyshev BP Filter
LTC1061
2
1061fe
OBSOLETE PACKAGE
Consider the N20 Package for Alternate Source
J PACKAGE
20-LEAD CERAMIC DIP
T
JMAX
= 125°C, θ
JA
= 100°C/W (J)
LTC1061AMJ
LTC1061MJ
LTC1061ACJ
LTC1061CJ
ELECTRICAL CHARACTERISTICS
(Complete Filter) The ● denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at VS = ±5V, TA = 25°C, T2L clock input level, unless otherwise specified.
1
2
3
4
5
6
7
8
9
10
TOP VIEW
N PACKAGE
20-LEAD PLASTIC DIP
20
19
18
17
16
15
14
13
12
11
LP
A
BP
A
N
A
INV
A
S1
A
AGND
50/100/HOLD
CLK
LS
h
V
+
LP
B
BP
B
N
B
INV
B
S1
B
V
–
LP
C
BP
C
HP
C
INV
C
SW PACKAGE
20-LEAD PLASTIC SO WIDE
ABSOLUTE AXI U RATI GS
W
WW
U
(Note 1)
WU
U
PACKAGE/ORDER I FOR ATIO
Supply Voltage ....................................................... 18V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1061AC, LTC1061C ............ –40°C ≤ T
A
≤ 85°C
LTC1061AM, LTC1061M ......... –55°C ≤ T
A
≤ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
LTC1061ACN
LTC1061CN
LTC1061CSW
ORDER PART
NUMBER
T
JMAX
= 100°C, θ
JA
= 100°C/W (N)
T
JMAX
= 100°C, θ
JA
= 85°C/W (SW)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Center Frequency Range, f
O
f
O
× Q ≤ 175kHz, Mode 1, V
S
= ±7.5V 0.1–35k Hz
f
O
× Q ≤ 1.6MHz, Mode 1, V
S
= ±7.5V 0.1–25k Hz
f
O
× Q ≤ 75kHz, Mode 3, V
S
= ±7.5V 0.1–25k Hz
f
O
× Q ≤ 1MHz, Mode 3, V
S
= ±7.5V 0.1–17k Hz
Input Frequency Range 0–200k Hz
Clock-to-Center Frequency Ratio, f
CLK
/f
O
Sides A, B: Mode 1, R1 = R3 = 50k
LTC1061A R2 = 5k, Q = 10, f
CLK
= 250kHz ●50±0.6%
LTC1061 Pin 7 High. ●50±1.2%
Side C: Mode 3, R1 = R3 = 50k
R2 = R4 = 5k, f
CLK
= 250kHz
LTC1061A Same as Above, Pin 7 at ●100±0.6%
LTC1061 Mid-Supplies, f
CLK
= 500kHz ●100±1.2%
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
LTC1061 1.2%
Q Accuracy Sides A, B, Mode 1
LTC1061A Side C, Mode 3 ●±25 %
LTC1061 f
O
× Q ≤ 50kHz, f
O
× ≤ 5kHz ●±35 %
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC1061
1061fe
Supply Voltage Range ±2.37 ±9V
Voltage Swings
LTC1061A V
S
= ±5V, R
L
= 5k (Pins 1,2,13,14,19,20) ±4.0 ±4.2 V
LTC1061 V
S
= ±5V, R
L
= 3.5k (Pins 3,12,18) ±3.8 ±4.2 V
LTC1061, LTC1061A ●±3.6 V
Output Short-Circuit Current
Source/Sink V
S
= ±5V 40/3 mA
DC Open-Loop Gain V
S
= ±5V, R
L
= 5k 80 dB
GBW Product V
S
= ±5V 3 MHz
Slew Rate V
S
= ±5V 7 V/µs
Center Frequency Range, f
O
f
O
× Q ≤ 120kHz, Mode 1, 50:1 0.1–12k Hz
f
O
× Q ≤ 120kHz, Mode 3, 50:1 0.1–10k Hz
Input Frequency Range 0 – 20k Hz
Clock-to-Center Frequency Ratio 50:1, f
CLK
= 250kHz, Q = 10
LTC1061A Sides A, B: Mode 1 50±0.6%
LTC1061 Side C, Mode 3, 250kHz 50±1.0%
LTC1061A 100:1, f
CLK
= 500kHz, Q = 10 100 ±0.6%
LTC1061 Sides A, B: Mode 1 100 ±1.0%
Side C: Mode 3
Q Accuracy
LTC1061A Same as Above ±2%
LTC1061 ±3%
Maximum Clock Frequency 700 kHz
Power Supply Current 4.5 6 mA
ELECTRICAL CHARACTERISTICS
(Complete Filter) The ● denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at VS = ±5V, TA = 25°C, T2L clock input level, unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
f
O
Temperature Coefficient Mode 1, 50:1, f
CLK
< 300kHz ±1ppm/°C
Q Temperature Coefficient Mode 1, 100:1, f
CLK
< 500kHz ±5ppm/°C
Mode 3, f
CLK
< 500kHz ±5ppm/°C
DC Offset Voltage
V
OS1
, Figure 23 ●215 mV
V
OS2
f
CLK
= 250kHz, 50:1 ●330 mV
V
OS2
f
CLK
= 500kHz, 100:1 ●660 mV
V
OS3
, LTC1061CN, ACN/LTC1061CS f
CLK
= 250kHz, 50:1 ●3 20/25 mV
V
OS3
, LTC1061CN, ACN/LTC1061CS f
CLK
= 500kHz, 100:1 ●6 40/50 mV
Clock Feedthrough f
CLK
< 1MHz 0.4 mV
RMS
Maximum Clock Frequency Mode 1, Q < 5, V
S
≥ ±5 2.5 MHz
Power Supply Current 6811 mA
●15 mA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
(Complete Filter) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are
at VS = ±2.37V, TA = 25°C, unless otherwise specified.
(Internal Op Amps) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C, unless otherwise specified.
LTC1061
4
1061fe
POWER SUPPLY VOLTAGE (±V)
0
ISUPPLY (mA)
8
1061 G09
6
3
024610
9
15
21
18
24
13579
27
30
12
TA = –55°C
TA = 25°C
TA = 125°C
CENTER FREQUENCY (kHz)
0
ERROR FROM IDEAL f
CLK
/f
O
(%)
32
1061 G08
1.0
0.5
0816 24 40
1.5
0
1.0
0.5
1.5
412
20 28 36
Q = 10
T
A
= 25°C
f
CLK
/f
O
= 50/1
MODE 1,
MODE 3
V
S
= ±2.5V
V
S
= ±7.5V
V
S
= ±5V
MODE 3
2.0
2.5
MODE 3
MODE 1
MODE 1
V
S
= ±2.5V
MODE 1,3
V
S
= ±5V
MODE 1,3
V
S
= ±7.5V
MODE 1,3
Q = 10
T
A
= 25°C
f
CLK
/f
O
= 100/1
CENTER FREQUENCY (kHz)
0
DEVIATION FROM IDEAL Q (%)
32
1061 G07
20
10
0816 24
30
0
20
10
30
412
20 28
Q=20
V
S
= ±2.5V V
S
= ±7.5V
20
10 10
V
S
= ±5V
Q=5
Q=20
Q=5
Q=1
10 Q=5
Q=1
CENTER FREQUENCY (kHz)
0
DEVIATION FROM IDEAL Q (%)
32
1061 G06
20
10
0816 24 40
30
0
20
10
30
412
20 28 36
TA = 25°C
fCLK/fO = 50/1
20
5Q=1
VS = ±2.5V
VS = ±7.5V
5
20
10
2010
TA = 25°C
fCLK/fO = 50:1 VS = ±5V
10
2.5
Q=1
52.5
Q=1
CENTER FREQUENCY (kHz)
0
DEVIATION FROM IDEAL Q (%)
32
1061 G05
20
10
0816 24
30
0
20
10
30
412
20 28
Q=20
VS = ±2.5V VS = ±7.5V
10
10
10
VS = ±5V
Q=5
Q<5 Q=20
Q=20 Q=5
CENTER FREQUENCY (kHz)
0
DEVIATION FROM IDEAL Q (%)
32
1061 G04
20
10
0816 24 40
30
0
20
10
30
412
20 28 36
T
A
= 25°C
f
CLK
/f
O
= 50/1
20
50 10
Q<5
V
S
= ±2.5V
V
S
= ±7.5V
50 20
10
Q<5
50 20
10 Q<5
T
A
= 25°C
f
CLK
/f
O
= 50/1 V
S
= ±5V
IDEAL Q
0.1
–0.2
DEVIATION OF f
CLK
/f
O
WITH RESPECT TO
Q = 10 MEASUREMENT (%)
–0.1
0
0.1
1 10 100
1061 G03
.
–0.3
–0.4
–0.5
V
S
= ±5V
T
A
= 25°C
PIN 7 AT 100:1
f
CLK
/f
O
= 500:1
√R2/R4 = 1/5
(A)
(B)
√R2/R4 = 1/2
f
CLK
/f
O
= 200:1
IDEAL Q
0.1
–0.3
% DEVIATION (f
CLK
/f
O
)
–0.2
–0.1
0
0.1
1 10 100
1061 G02
.
–0.4
–0.5
–0.6
V
S
= ±5V
T
A
= 25°C
f
CLK
= 500kHz
f
CLK
/f
O
=
100 (TEST POINT)
IDEAL Q
0.1
–1.6
% DEVIATION (f
CLK
/f
O
)
–1.2
–0.8
–0.4
0
1 10 100
1061 G01
–2.0
–2.4
0.4 V
S
= ±5V
T
A
= 25°C
f
CLK
= 250kHz
f
CLK
/f
O
=
50 (TEST POINT)
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Mode 1, Mode 3 (fCLK/fO)
Deviation vs Q
Mode 1, Mode 3 (fCLK/fO)
Deviation vs Q
Mode 3: Deviation of (fCLK/fO)
with Respect to Q = 10
Measurement
Mode 1: (fCLK/fO) = 50:1 Mode 1: (fCLK/fO) = 100:1 Mode 3: (fCLK/fO) = 50:1
Mode 3: (fCLK/fO) = 100:1 fCLK/fO vs fO
Power Supply Current vs
Supply Voltage
5
LTC1061
1061fe
DESCRIPTIO A D
U
PI
U
APPLICATIO
U
HI TS
UU
–
+
Σ+∫
Σ
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
CLOCK
GENERATOR
CLOCK
GENERATOR
CLOCK
GENERATOR
CLK
(8)
LEVEL SHIFT
(9)
TO FILTER A
TO FILTER B
TO FILTER C
+∫
+∫
+∫
+∫
+∫
50/100/
HOLD
(7)
AGND
(6)
V
+
(10)
V
–
(15)
HP
C
(12)
S1
B
(16)
BP
C
(13)
LP
C
(14)
S1
A
(5)
NB
(18)
BP
B
(19)
LP
B
(20)
NA
(3)
BP
A
(2)
LP
A
(1)
INV
A
(4)
INV
B
(17)
INV
C
(11)
1061 BD
+
–
+
–
–
+
–
+
frequencies below 500kHz the clock “on” time can be as
low as 300ns. The maximum clock frequency for ±5V
supplies and above is 2.4MHz.
S1
A
, S1
B
(Pins 5, 16)
These are voltage input pins. If used, they should be driven
with a source impedance below 5kΩ. when they are not
used, they should be tied to the analog ground Pin 6.
AGND (Pin 6)
When the LTC1061 operates with dual supplies, Pin 6
should be tied to system ground. When the LTC1061
operates with a single positive supply, the analog ground
pin should be tied to 1/2 supply, Figure 1. The positive
input of all the internal op amps, as well as the common
reference of all the internal switches, are internally tied to
the analog ground pin. Because of this, a “clean” ground
is recommended.
Power Supplies (Pins 10, 15)
They should be bypassed with 0.1µF disc ceramic. Low
noise, nonswitching, power supplies are recommended.
The device operates with a single 5V supply, Figure 1, and
with dual supplies. The absolute maximum operating
power supply voltage is ±9V.
Clock and Level shift (Pins 8, 9)
When the LTC1061 operates with symmetrical dual sup-
plies the level shift Pin 9 should be tied to analog ground.
For single 5V supply operation, the level shift pin should be
tied to Pin 15 which will be the system ground. The typical
logic threshold levels of the clock pin are as follows: 1.65V
above the level shift pin for ±5V supply operation, 1.75V
for ±7.5V and above, and 1.4V for single 5V supply
operation. The logic threshold levels vary ±100mV over
the full military temperature range. The recommended
duty cycle of the input clock is 50% although for clock
BLOCK DIAGRA
W
LTC1061
6
1061fe
Figure 1. The 6th Order LP Butterworth Filter of Figure 5
Operating with a Single 5V Supply
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R3
V
OUT
R1
V
IN
0.1µF
1061 F01
LTC1061
+
R2
R1
R3
R2
R4
R1
R3
R2
T
2
L CLOCK
IN
f
CLK
< 1MHz
1µF
5V
2.49k
2.49k
C
IN
Clock Feedthrough
This is defined as the amplitude of the clock frequency
appearing at the output pins of the device, Figure 2. Clock
feedthrough is measured with all three sides of the LTC1061
connected as filters. The clock feedthrough mainly de-
pends on the magnitude of the power supplies and it is
independent from the input clock levels, clock frequency
and modes of operation.
The Table 2 illustrates the typical clock feedthrough num-
bers for various power supplies.
50/100/Hold (Pin 7)
By tying Pin 7 to V
+
, the filter operates with a clock-to-
center frequency internally set at 50:1. When Pin 7 is at
mid-supplies, the filter operates with a 100:1 clock-to-
center frequency ratio. Table 1 shows the allowable varia-
tion of the potential at Pin 7 when the 100:1 mode is
sought.
When Pin 7 is shorted to the negative supply pin, the filter
operation is stopped and the bandpass and lowpass
output act as a sample-and-hold circuit holding the last
sample of the input voltage. The hold step is around 2mV
and the droop rate is 150µV/sec.
Table 1
TOTAL POWER SUPPLY VOLTAGE RANGE OF PIN 7
(V) FOR 100:1 OPERATION (V)
5 2.5 ± 0.5
10 5 ±1
15 7.5 ±1.5
Figure 2. Typical Clock Feedthrogh of the LTC1061 Operating
with ±5V Supplies. Top Trace is the Input Clock Swinging 0V to
5V and Bottom Trace is One of the Lowpass Outputs with Zero or
DC Input Signals.
A = 2V/DIV
B = 10mV/DIV
HORIZONTAL = 10µs/DIV
POWER SUPPLY (V) CLOCK FEEDTHROUGH (V
RMS
)
±2.5 0.2
±5 0.4
±8 0.8
Table 2
Definition of Filter Functions
Refer to LTC1060 data sheet.
1061 F02
DESCRIPTIO A D
U
PI
U
APPLICATIO
U
HI TS
UU
7
LTC1061
1061fe
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R32
V
OUT
R13
V
IN
LTC1061 F05
LTC1061
R22
R12
R31
R21
R41
R33
R23
T
2
L CLOCK
< 2.5MHz
V
–
R11
V
+
HARMONIC DISTORTION WITH f
CLK
= 2MHz
f
IN
2ND HARMONIC
10kHz, 1V
RMS
20kHz, 1V
RMS
30kHz, 1V
RMS
40kHz, 1V
RMS
–74dB
–62dB
–62dB
–62dB
STANDARD 1%
RESISTOR VALUES
R11 = 20k
R31 = 11k
R12 = 20k
R32 = 14k
R13 = 10k
R21 = 20k
R41 = 20k
R22 = 20k
R23 = 10k
R33 = 17.8k
–
+
Σ∫∫
AGND
R1
HP BP LP
V
IN
1061 F04
+–
S
1/3 LTC1061
R2
R3
R4
C
C
NOTE: ADD C
C
FOR Q > 5 AND f
CLK
> 1MHz, SUCH AS C
C
≅ 0.16
R4 × 1.2MHz
f
O
= ; Q =
H
OHP
= – ; H
OBP
= – ; H
OLP
= –
f
CLK
100(50)
R2
R1
R3
R1
R4
R1
R3
R2
√
R2
R4
√
R2
R4
–
+
Σ∫∫
AGND
R1
NBP LP
V
IN
1061 F03
+–
S
1/3 LTC1061
R2
R3
f
O
= ; f
n
= f
O
H
OLP
= – ; H
OBP
= – ; H
ON1
= –
Q =
f
CLK
100(50)
R2
R1
R3
R1
R2
R1
R3
R2
ODES OF OPERATIO
W U
Description and Applications
1. Primary Modes: There are two basic modes of opera-
tion, Mode 1 and Mode 3. In Mode 1, the ratio of the
external clock frequency to the center frequency of each
2nd order section is internally fixed at 50:1 or 100:1. In
Mode 3, this ratio can be adjusted above or below 50:1 or
100:1. The side C of the LTC1061 can be connected only
in Mode 3. Figure 3 illustrates Mode 1 providing 2nd order
notch, lowpass, and bandpass outputs (for definition of
filter functions, refer to the LTC1060 data sheet). Mode 1
can be used to make high order Butterworth lowpass
filters; it can also be used to make low Q notches and for
cascading 2nd order bandpass functions tuned at the
same center frequency and with unity-gain. Mode 3,
Figure 4, is the classical state variable configuration pro-
viding highpass, bandpass and lowpass 2nd order filter
functions.
Since the input amplifier is within the resonant loop, its
phase shift affects the high frequency operation of the
filter and therefore, Mode 3 is slower than Mode 1. Mode
3 can be used to make high order all-pole bandpass,
lowpass, highpass and notch filters. Mode 3 as well as
Mode 1 is a straightforward mode to use and the filter’s
dynamics can easily be optimized. Figure 5 illustrates a 6th
order lowpass Butterworth filter operating with up to
40kHz cutoff frequency and with up to 200kHz input
frequency. Sides A, B are connected in Mode 1 while side
C is connected in Mode 3. The lower Q section was placed
in side C, Mode 3, to eliminate any early Q enhancement.
This could happen when the clock approaches 2MHz. The
measured frequency response is shown in Figure 6. The
attenuation floor is limited by the crosstalk between the
three different sections operating with a clock frequency
above 1MHz. The measured wideband noise was
150µV
RMS
. For limited temperature range the filter of
Figure 5 works up to 2.5MHz clock frequency thus yielding
a 50kHz cutoff.
Figure 4. Mode 3: 2nd Order Filter Providing Highpass,
Bandpass, Lowpass
Figure 3. Mode 1: 2nd Order Filter Providing Notch,
Bandpass, Lowpass
Figure 5. 6th Order Butterworth Lowpass Filter with
Cutoff Frequency up to 45kHz
LTC1061
8
1061fe
f
IN
(Hz)
10k
–70
V
OUT
/V
IN
(dB)
–60
–50
–40
–30
100k 1M
1061 F09
–20
–10
0
30k
V
S
> ±5V
T
A
= 25°C
V
IN
= 1V
RMS
f
CLK
= 1.9MHz
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R32
VOUT
R11
VIN
1061 F08
LTC1061
R22
R12
R33
R23
R43
R31
R21
fCLK < 2MHz
V–
R13
V+
R51
R61
STANDARD 1% RESISTOR VALUES
R11 = 35.7k
R31 = 11.5k
R51 = 5.49k
R12 = 11k
R61 = 2.87k
R22 = 11k
R23 = 10.5
R43 = 15.8k
R32 = 36.5k
R13 = 15.8k
R33 = 13k
R21 = 12.1k
–
+
Σ∫∫
AGND
R1
NBP LP
V
IN
1061 F07
+–
S
R2
R3
R6 R5
f
O
= ; f
n
= f
O
; Q =
H
ON1
(f → 0) = H
ON2
= –
H
OLP
= ; H
OBP
= – ; (R5//R6) <5k
f
CLK
100(50)
R2
R1
R3
R2
–R2/R1
R6/(R5 + R6)
R3
R1
√
R6
R5 + R6
√
R6
R5 + R6
f
CLK
2
f →
()
ODES OF OPERATIO
W U
Figure 6. Measures Frequency Response of
the Lowpass Butterworth Filter of Figure 3
2. Secondary Modes: Mode 1b – It is derived from Mode
1. In Mode 1b, Figure 7, two additional resistors, R5 and
R6, are added to attenuate the amount of voltage fed back
from the lowpass output into the input of the S
A
(S
B
)
switched capacitor summer. This allows the filter clock-
to-center frequency ratio to be adjusted beyond 50:1 (or
100:1). Mode 1b still maintains the speed advantages of
Mode 1. Figure 8 shows the 3 lowpass sections of the
LTC1061 in cascade resulting in a Chebyshev lowpass
filter. The side A of the IC is connected in Mode 1b to
provide the first resonant frequency below the cutoff
frequency of the filter. The practical ripple, obtained by
using a non-A version of the LTC1061 and 1% standard
resistor values, was 0.15dB. For this 6th order lowpass,
the textbook Qs and center frequencies normalized to the
ripple bandwidth are: Q1 = 0.55, f
O1
= 0.71, Q2 = 1.03, F
O2
= 0.969, Q3 = 3.4, F
O3
= 1.17. The design was done with
speed in mind. The higher (Q3, F
O3
) section was in Mode
1 and placed in the side B of the LTC1061. The remaining
two center frequencies were then normalized with respect
to the center frequency of side B; this changes the ratio of
clock-to-cutoff frequency from 50:1 to 50 × 1.17 = 58.5:1.
As shown in Figure 9, the maximum cutoff frequency is
about 33kHz. The total wideband output noise is 220µV
RMS
and the measured output DC offset voltage is 60mV.
Figure 8. 6th Order Chebyshev, Lowpass Filter Using 3
Different Modes of Operation for Speed Optimization
Figure 9. Amplitude Response of the 6th Order
Chebyshev Lowpass Filter of Figure 8
Figure 7. Mode 1b: 2nd Order Filter Providing
Notch, Bandpass, Lowpass
fIN (Hz)
10k
–70
GAIN (dB)
–60
–50
–40
–30
100k 1M
1061 F06
–20
–10
0
20k 40k 200k
VS ≥ ±5V
TA = 25°C
VIN = 1VRMS
fCLK = 2MHz
fC = 40kHz
fCLK = 1MHz
fC = 20kHz
9
LTC1061
1061fe
–
+
Σ∫∫
AGND
R1
HP BP LP
VIN
1061 F11
+–
S
R2
R3
R4
CC
NOTE: FOR Q > 5 AND fCLK > 1MHz, ADD CC SUCH AS CC ≅
–
+
EXTERNAL OP AMP OR
INPUT OP AMP OF THE
LTC1061, SIDES A, B, C
NOTCH
Rg
Rl
Rh
R2
R1
R3
R2
R4
R1
R4
R1
fO = ; fn = ; HOHP = – ; HOBP = – ; HOLP = –
HON1 (f → 0) = × ; HON2 = × ; HON (f = fO) = Q HOLP – HOHP
Q =
fCLK
100(50)
R2
R1
R3
R1
√
R2
R4
fCLK
2
f →
()
fCLK
100(50)
√
Rh
Rl
Rg
Rl
Rg
Rh
()
Rg
Rl
Rg
Rh
R2
R4
0.16
R4 × 1.2MHz
√
MODE 1b MODE 1 MODE 3
SIDE A SIDE B SIDE C
VIN VOUT
fO1 = 0.95
Q1 = 31.9
fO2 = 1.05
Q2 = 31.9
fO3 = 1
Q3 = 15.9
1061 F10b
MODE 1b MODE 1 MODE 3
SIDE A SIDE B SIDE C
VIN VOUT
fO1 = 0.95
Q1 = 31.9
fO2 = 1
Q2 = 15.9
fO3 = 1.05
Q3 = 31.9
1061 F10a
Another example of Mode 1b is illustrated on the front
page of the data sheet. The cascading sequence of this 6th
order bandpass filter is shown in block diagram form,
Figure 10a. the filter is geometrically centered around the
side B of the LTC1061 connected in Mode 1. This dictates
a clock-to-center frequency ratio of 50:1 or 100:1. The side
A of the IC operates in Mode 1b to provide the lower center
frequency of 0.95 and still share the same clock with the
rest of the filter. With this approach the bandpass filter can
operate with center frequencies up to 24kHz. The speed of
the filter could be further improved by using Mode 1 to lock
the higher resonant frequency of 1.05 and higher Q or 31.9
to the clock, Figure 10b, thus changing the clock to center
frequency ratio to 52.6:1.
Mode 3a – This is an extension of Mode 3 where the
highpass and lowpass outputs are summed through two
external resistors R
h
and R
l
to create a notch, Figure 11.
Mode 3a is very versatile because the notch frequency can
be higher or lower than the center frequency of the 2nd
order section. The external op amp of Figure 11 is not
always required. When cascading the sections of the
LTC1061, the highpass and lowpass outputs can be
summed directly into the inverting input of the next
section. Figure 12 shows an LTC1061 providing a 6th
order elliptic bandpass or notch response. Sides C and B
are connected in Mode 3a while side A is connected in
Mode 1 and uses only two resistors. The resulting filter
response is then geometrically symmetrical around either
the center frequency of side A (for bandpass responses) or
the notch frequency of side A (for notch responses).
Figure 11. Mode 3a: 2nd Order Filter Providing Highpass, Bandpass, Lowpass, Notch
ODES OF OPERATIO
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Figure 10a. Cascading Sequence of the Bandpass Filter Shown
on the Front Page, with (fCLK/fO) = 50:1 or 100:1
Figure 10b. Cascading Sequence of the Same Filter for Speed
Optimization, and with (fCLK/fO) = 52.6:1
LTC1061
10
1061fe
fIN (kHz)
1.0
VOUT/VIN (dB)
–10
3.0
1061 F14
–30
–60
–80
1.5 2.0 2.5 3.5
–50
–40
–20
0
–70
–90
VS = ±5V
fCLK = 130kHz R11 = 576k
R31 = 562k
Rh11 = 28.7k
R22 = 10.7k
R42 = 10k
Rl2 = 10k
R33 = 75k
R21 = 10k
R41 = 10.7k
Rl11 = 40.2k
R32 = 562k
Rh2 = 14k
R23 = 2.94k
NOTE: FOR CLOCK FREQUENCIES
ABOVE 500kHz, CONNECT A 5pF
IN PARALLEL WITH R41 AND R42.
STANDARD 1%
RESISTOR VALUES
f
IN
(kHz)
1.0
V
OUT
/V
IN
(dB)
–10
3.0
1061 F13
–30
–60
–70 1.5 2.0 2.5 3.5
–50
–40
–20
0BW1
BW2
2.6kHz
STANDARD 1%
RESISTOR VALUES
R11 = 165k
R31 = 143k
R
h
1 = 10k
R22 = 20k
R42 = 15.4k
R
l
2 = 10k
R33 = 169k
R21 = 10k
R41 = 13k
R
l
1 = 10.5k
R32 = 221k
R
h
2 = 10.5k
R23 = 84.5k
NOTES: USE A 15pF CAPACITOR
BETWEEN PINS 17 AND 18.
PIN 7 IS GROUNDED.
V
S
= ±5V
f
CLK
= 260kHz
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R32
VIN
1061 F12
LTC1061
R22
R
h
2
R31
R41
R33
R23
T
2
L, CMOS
CLOCK INPUT
V
–
R42
V
+
NOTES: FOR NOTCH RESPONSES, PIN 7 SHOULD BE
PREFERABLY CONNECTED TO GROUND AND THE
FILTER OUTPUT IS PIN 3.
FOR BANDPASS OR LOWPASS RESPONSES, PIN 7
CAN BE EITHER AT GROUND OR POSITIVE SUPPLY,
AND THE FILTER OUTPUT IS PIN 2 OR PIN 1.
R
l
2
R
l
1
R21
R11
R
h
1
ODES OF OPERATIO
W U
center frequencies, Qs, and notch frequencies are (f
O1
=
0.969, Q1 = 54.3, f
n1
= 0.84, f
O2
= 1.031, Q2 = 54.3, f
n2
=
1.187, f
O3
= 1, Q3 = 26.2). The output of the filter is the BP
output of Side A, Pin 2.
Lowpass filters with stopband notches can also be realized
by using Figure 12 provided that 6th order lowpass filter
approximations with 2 stopband notches can be synthe-
sized. Literature describing elliptic double terminated (RLC)
Figure 14. Resistor Values and Amplitude Response of Figure 12
Topology. The Bandpass Filter is Centered Around 2600Hz when
Operating with a 130kHz Clock.
Figure 13. Resistor Values and Amplitude Response of
Figure 12 Topology. The Notch is Centered at 2600Hz.
Figure 12. 6th Order Elliptic Bandpass, Lowpass
or Notch Topology
Figure 13 shows the measured frequency response of the
circuit Figure 12 configured to provide a notch function.
The filter output is taken out of pin 3. The resistor values
are standard 1%.
The ratio of the 0dB width, BW1, to the notch width BW2,
is 5:1 and matches the theoretical design value. The
measured notch depth was –53dB versus –56dB theoreti-
cal and the clock-to-center notch frequency ratio is 100:1.
Figure 14 shows the measured frequency response of the
circuit topology, Figure 12, but with pole/zero locations
configured to provide a high Q, 6th order elliptic bandpass
filter operating with a clock-to-center frequency ratio of
50:1 or 100:1. The theoretical passband ripple, stopband
attenuation and stopband to ripple bandwidth ratio are
0.5dB, 56dB, 5:1 respectively. The obtained results with
1% standard resistor values closely match the theoretical
frequency response. For this application, the normalized
11
LTC1061
1061fe
fIN (kHz)
0
VOUT/VIN (dB)
–10
2.0
1061 F17
–30
–60
–80
0.5 1.0 1.5 2.5
–50
–40
–20
0
–70
–90
fCLK = 250kHz
R11 = 105k
R31 = 47.5k
Rh1 = 10k
R22 = 32.4k
R42 = 52.3k
Rl2 = 750k
R33 = 255k
Rh3 = 10k
Rg = 140k
R21 = 10k
R41 = 45.3k
Rl1 = 1.07M
R32 = 28.7k
Rh2 = 42.2k
R23 = 10k
R43 = 63.4k
Rl3 = 110k
NOTE: FOR CLOCK FREQUENCIES
BELOW 500kHz, USE A CAPACI-
TOR IN PARALLEL WITH R21
SUCH AS (1/2πR21C) ≅ fCLK/3.
STANDARD 1%
RESISTOR VALUES
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
V
IN
1061 F16
LTC1061
R
h
2
R43
R33
T
2
L
l
, CMOS
CLOCK INPUT
V
–
V
+
R
l
2
R32
R22
R42
R31
R41
R
l
1
R21
R11
R
h
1
R
l
3
R
h
3
R23
–
+
V
OUT
R
g
LT1056
f
IN
(kHz)
1
V
OUT
/V
IN
(dB)
–10
9
1061 F15
–30
–60
–80
357
0
–50
–40
–20
0
–70
–90 246810
STANDARD 1%
RESISTOR VALUES
R11 = 39.2k
R31 = 13.7k
R
h
1 = 20.5k
R22 = 10k
R42 = 14k
R
l
2 = 11.8k
R33 = 100k
R21 = 10k
R41 = 39.2k
R
l
1 = 12.4k
R32 = 26.7k
R
h
2 = 32.4k
R23 = 10k
NOTES: USE A 10pF ACROSS R42
FOR f
CLK
> 1MHz.
THE ELLIPTIC LOWPASS FILTER
HAS ONLY TWO NOTCHES IN THE
STOPBAND, AND IT OPERATES
WITH A CLOCK TO CUTOFF
FREQUENCY RATIO OF 50:1.
Figure 17. Measured Amplitude Response of the Topology of
Figure 16, Configured to Provide a 6th Order Elliptic Highpass
Filter Operating with a Clock-to-Cutoff Frequency Ratio of 250:1
ODES OF OPERATIO
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Figure 15. Resistor Values and Amplitude Response of
the Topology of Figure 12
passive ladder filters provide enough data to synthesize
the above filters. The measured amplitude response of
such a lowpass is shown in Figure 15 where the filter
output is taken out of side A’s Pin 1, Figure 12. The clock-
to-center frequency ratio can be either 50:1 or 100:1
because the last stage of the LTC1061 operates in Mode 1
with a center frequency very close to the overall cutoff
frequency of the lowpass filter.
In Figure 16, all three sides of the LTC1061 are connected
in Mode 3a. This topology is useful for elliptic highpass
and notch filters with clock-to-cutoff (or notch) frequency
ratio higher than 100:1. This is often required to extend the
allowed input signal frequency range and to avoid prema-
ture aliasing. Figure 16 is also a versatile, general purpose
architecture providing 3 notches and 4 pole pairs, and
there is no restriction on the location of the poles with
respect to the notch frequencies. The drawbacks, when
compared to Figure 12, are the use of an external op amp
and the increased number of the required external
resistors.
Figure 17 shows the measured frequency of a 6th order
highpass elliptic filter operating with 250:1 clock-to-cutoff
frequency ratio. With a 1MHz clock, for instance, the filter
yields a 4kHz cutoff frequency, thus allowing an input
frequency range beyond 100kHz. Band limiting can be
easily added by placing a capacitor across the feedback
resistor of the external op amp of Figure 16.
Figure 16. Using an External Op Amp to Connect
all 3 Sides of the LTC1061 in Mode 3a
LTC1061
12
1061fe
+
Σ∫∫
AGND
R1
NBP LP
V
IN
1061 F20
+–
S
R2
R3
R4
f
O
= ; f
n
= ; Q =
H
OLP
= ; H
OBP
= –
H
ON1
(f → 0) = ; H
ON2
= –
f
CLK
100(50)
R2
R1
R3
R2
–R2/R1
1 + (R2/R4)
R3
R1
f
CLK
2
f →
()
√
1 + R2
R4
f
CLK
100(50)
√
1 + R2
R4
–R2/R1
1 + (R2/R4)
–
f
IN
(kHz)
1
0
V
OUT
/V
IN
(dB)
–90
–50
–30
–10
10 100
1061 F19
–80
–70
–60
–40
–20
4
STANDARD 1%
RESISTOR VALUES
R11 = 30.9k
R31 = 16.2k
R
h
1 = 45.3k
R22 = 10.5k
R42 = 10k
R
l
2 = 15.8k
R33 = 28.7k
R
h
3 = 95.3k
R
g
= 28k
R21 = 10k
R41 = 26.7k
R
l
1 = 19.6k
R32 = 100k
R
h
2 = 52.3k
R23 = 10k
R43 = 12.7k
R
l
3 = 10k
NOTE: ADD A CAPACITOR C ACROSS R
g
TO CREATE A 7TH ORDER
LOWPASS SUCH AS (1/2πR
g
C) = (CUTOFF FREQUENCY) × 0.38
f
CLK
200kHz
f
CLK
500kHz
f
CLK
1MHz
fIN (kHz)
0
VOUT/VIN (dB)
–10
1.6
1061 F18
–30
–60
–70 0.2 0.8 1.2 2.0
–50
–40
–20
0
fCLK = 250kHz
0.4 0.6 1.0 1.4 1.8
STANDARD 1%
RESISTOR VALUES
R11 = 84.5k
R31 = 31.6k
Rh1 = 48.7k
R22 = 10k
R42 = 97.6k
Rl2 = 66.5k
R33 = 300k
Rh3 = 10.2k
Rg = 210k
R21 = 10.2k
R41 = 63.4k
Rl1 = 287k
R32 = 232k
Rh2 = 10.2k
R23 = 20k
R43 = 80.6k
Rl3 = 63.4k
NOTE: CONNECT 39pF AND
100pF ACROSS R21 AND R22
RESPECTIVELY.
ODES OF OPERATIO
W U
Mode 2 – This is a combination of Mode 1 and Mode 3,
Figure 20. With Mode 2, the clock-to-center frequency
ratio, f
CLK
/f
O
, is always less than 50:1 or 100:1. When
compared to Mode 3 and for applications requiring 2nd
order section with f
CLK
/f
O
slightly less than 100 or 50:1,
Mode 2 provides less sensitivity to resistor tolerances. As
in Mode 1, Mode 2 has a notch output which directly
depends on the clock frequency and therefore the notch
frequency is always less than the center frequency, f
O
, of
the 2nd order section.
Figure 18 shows the plotted amplitude responses of a 6th
order notch filter operating again with a clock-to-center
notch frequency ratio of 250:1. The theoretical notch
depth is 70dB and when the notch is centered at 1kHz its
width is 50Hz. Two small, noncritical capacitors were used
across the R21 and R22 resistors of Figure 16, to band-
limit the first two highpass outputs such that the practical
notch depth will approach the theoretical value. With these
two fixed capacitors, the notch frequency can be swept
within a 3:1 range.
When the circuit of Figure 16 is used to realize lowpass
elliptic filters, a capacitor across R
g
raises the order of the
filter and at the same time eliminates any small clock
feedthrough. This is shown in Figure 19 where the ampli-
tude response of the filter is plotted for 3 different cutoff
frequencies. When the clock frequency equals or exceeds
1MHz, the stopband notches lose their depth due to the
finite bandwidth of the internal op amps and to the small
crosstalk between the different sides of the LTC1061. The
lowpass filter, however, does not lose its passband accu-
racy and it maintains nearly all of its attenuation slope. The
theoretical performance of the 7th order lowpass filter of
Figure 19 is 0.2dB passband ripple, 1.5:1 stopband-to-
cutoff frequency ratio, and 73dB stopband attenuation.
Without any tuning, the obtained results closely approxi-
mate the textbook response.
Figure 19. Frequency Responses of a 7th Order Lowpass Elliptic
Filter Realized with Figure 16 Topology
Figure 18. 6th Order Band Reject Filter Operating with a Clock-
to-Center Notch Frequency Ratio of 250:1. The Ratio of 0dB to
the –65dB Notch Width is 8:1.
Figure 20. Mode 2: 2nd Order Filter Providing
Notch, Bandpass, Lowpass
13
LTC1061
1061fe
fIN (kHz)
1
VOUT/VIN (dB)
–10
9
1061 F22
–30
–60
–80
357
0
–50
–40
–20
0
–70
–90 246810
STANDARD 1%
RESISTOR VALUES
R11 = 54.9k
R31 = 34.8k
Rh1 = 28.7k
R22 = 68.1k
R42 = 10k
Rl2 = 16.2k
R33 = 75k
R21 = 24.3k
R41 = 10k
Rl1 = 280k
R32 = 18.2k
Rh2 = 10.2k
R23 = 10k
R43 = 14k
NOTE: FOR CLOCK FREQUEN-
CIES ABOVE 300kHz, ADD
A CAPACITOR C ACROSS
R21 AND R22 SUCH AS
(1/2πR21C) = fCLK
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
V
IN
1061 F21
LTC1061
R
h
2
R43
R33
T
2
L, CMOS
CLOCK INPUT
V
–
V
+
R
l
2
R32
R22
R42
R31
R41
R
l
1
R21
R11
R
h
1
R23
V
OUT
ODES OF OPERATIO
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higher frequency notch provided by the side A of the
LTC1061. As shown in Figure 22, the highpass corner
frequency is 3.93kHz and the higher notch frequency is
3kHz while the filter operates with a 300kHz clock. The
center frequencies, Qs, and notches of Figure 22, when
normalized to the highpass cutoff frequency, are (f
O1
=
1.17, Q1 = 2.24, f
n1
= 0.242, f
O2
= 1.96, Q2 = 0.7, f
n2
= 0.6,
f
O3
= 0.987, f
n3
= 0.753, Q3 = 10). When compared with the
topology of Figure 16, this approach uses lower and more
restricted clock frequencies. The obtained notch in Mode
2 is shallower although the topology is more efficient.
Output Noise
The wideband RMS noise of the LTC1061 outputs is nearly
independent from the clock frequency. The LTC1061
noise when operating with ±2.5V supply is lower, as Table
3 indicates. The noise at the bandpass and lowpass
outputs increases rough as the √Q. Also the noise in-
creases when the clock-to-center frequency ratio is al-
tered with external resistors to exceed the internally set
100:1 or 50:1 ratios. Under this condition, the noise
increases square root-wise.
Output Offsets
The equivalent input offsets of the LTC1061 are shown in
Figure 23. The DC offset at the filter bandpass output is
always equal to V
OS3
. The DC offsets at the remaining two
outputs (Notch and LP) depend on the mode of operation
and external resistor ratios. Table 4 illustrates this.
It is important to know the value of the DC output offsets,
especially when the filter handles input signals with large
dynamic range. As a rule of thumb, the output DC offsets
increase when:
1. The Qs decrease
2. The ratio (f
CLK
/f
O
) increases beyond 100:1. This is
done by decreasing either the (R2/R4) or the R6/(R5
+ R6) resistor ratios.
Figure 21 shows the side A of the LTC1061 connected in
Mode 2 while sides B and C are in Mode 3a. This topology
can be used to synthesize elliptic bandpass, highpass and
notch filters. The elliptic highpass of Figure 17 is synthe-
sized again, Figure 22, but the clock is now locked onto the
Figure 22. 6th Order Elliptic Highpass Filter Operating with a
Clock-to-Cutoff Frequency Ratio of 75:1 and Using the Topology
of Figure 21
Figure 21. LTC1061 with Side A is Connected in Mode 2 While
Side B, C are in Mode 3a. Topology is Useful for Elliptic
Highpass, Notch and Bandpass Filters.
LTC1061
14
1061fe
–
+
1061 F23
+
–
VOS2
VOS1
Σ
(12,18)
3
5
+––
+
VOS3
2
+––
+
1
6
(13,19) (14,20)
(11,17)
+–
4
ODES OF OPERATIO
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NOTCH/HP BP LP
V
S
(±V) f
CLK/
f
O
(µV
RMS
)(µV
RMS
)(µV
RMS
) CONDITIONS
5.0 50:1 45 55 70 Mode 1, R1 = R2 = R3
5.0 100:1 65 65 85 Q = 1
2.5 50:1 30 30 45
2.5 100:1 40 40 60
5.0 50:1 18 150 150 Mode 1, Q = 10
5.0 100:1 20 200 200 R1 = R3 for BP Out
2.5 50:1 15 100 100 R1 = R2 for LP Out
2.5 100:1 17 140 140
5.0 50:1 57 57 62 Mode 3, R1 = R2 = R3 = R4
5.0 100:1 72 72 80 Q = 1
2.5 50:1 40 40 42
2.5 100:1 50 50 53
5.0 50:1 135 120 140 Mode 3, R2 = R4, Q = 10
5.0 100:1 170 160 185 R3 = R1 for BP Out
2.5 50:1 100 88 100 R4 = R1 for LP and HP Out
2.5 100:1 125 115 130
Table 3. Wideband RMS Noise
Figure 23. Equivalent Input Offsets of 1/3 LTC1061 Filter Building Block
V
OSN
V
OSBP
V
OSLP
MODE PIN 3 (18) PIN 2 (19) PIN 1 (20)
1V
OS1
[(1/Q) + 1 + || H
OLP
||] – V
OS3
/Q V
OS3
V
OSN
–
V
OS2
1b V
OS1
[(1/Q) + 1 + R2/R1] – V
OS3
/Q V
OS3
~(V
OSN
–
V
OS2
)(1 + R5/R6)
2[V
OS1
(1 + R2/R1 + R2/R3 + R2/R4) – V
OS3
(R2/R3)] ×V
OS3
V
OSN
–
V
OS2
× [R4/(R2 + R4)] + V
OS2
[R2/(R2 + R4)]
3V
OS2
V
OS3
V
OS1
(1 + R4/R1 + R4/R2 + R4/R3) – V
OS2
(R4/R2)
– V
OS3
(R4/R3)
Table 4
15
LTC1061
1061fe
N Package
20-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
OBSOLETE PACKAGE
J20 0801
37
56 109
142 8
11
20 16 1517 14 13 1219 18
.005
(0.127)
MIN
.025
(0.635)
RAD TYP
.220 – .310
(5.588 – 7.874)
1.060
(26.924)
MAX
0° – 15°
.008 – .018
(0.203 – 0.457)
.015 – .060
(0.381 – 1.524)
.125
(3.175)
MIN
.014 – .026
(0.356 – 0.660)
.045 – .065
(1.143 – 1.651) .100
(2.54)
BSC
.200
(5.080)
MAX
.300 BSC
(7.62 BSC)
.045 – .065
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
J Package
20-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
N20 0405
.020
(0.508)
MIN
.120
(3.048)
MIN
.125 – .145
(3.175 – 3.683)
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.018 ± .003
(0.457 ± 0.076)
.005
(0.127)
MIN
.255 ± .015*
(6.477 ± 0.381)
1.060*
(26.924)
MAX
12345678910
19 1112
131416 1517
18
20
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
LTC1061
16
1061fe
S20 (WIDE) 0502
NOTE 3
.496 – .512
(12.598 – 13.005)
NOTE 4
20
N
19 18 17 16 15 14 13
12345678
.394 – .419
(10.007 – 10.643)
910
N/2
1112
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC
.014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
123 N/2
.050 BSC
.030 ±.005
TYP
.005
(0.127)
RAD MIN
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LT/LT 0905 REV E • PRINTED IN USA
PACKAGE DESCRIPTIO
U
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1068 Quad, Universal, Filter Building Block 25:1, 50:1, 100:1, 200:1 F
C
:F
CLK
Ratios Available
LTC1562 Quad, Universal, Filter Building Block Continuous Time, Active RC, F
C
< 150kHz
LTC1562-2 Quad, Universal, Filter Building Block Continuous Time, Active RC, F
C
< 360kHz
© LINEAR TECHNOLOGY CORPORATION 1994
