October 2006
Communication Solutions
Preliminary
Data Sheet
Revision 2.0
SLIC-E / TSLIC-E
Subscriber Line Interface Circuit Enhanced Feature Set
SLIC-E (PEF 4265), Version 2.1
SLIC-E2 (PEF 4265-2), Version 2.1
TSLIC-E (PEF 4365), Version 2.1
Edition 2006-10-10
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Preliminary Data Sheet 3 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Trademarks
ABM®, ACE®, AOP®, Arcofi®, ASM®, ASP®, BlueMoon®, BlueNIX®, C166®, DuSLIC®, ELIC®, Epic®, FALC®,
GEMINAX®, Idec®, INCA®, IOM®, Ipat®-2, IPVD®, Isac®, Itac®, IWE®, IWORX®, M-GOLD®, MUSAC®, MuSLIC®,
OCTALFALC®, OCTAT®, POTSWIRE®, QUADFALC®, QUAT®, SCOUT®, SCT®, SEROCCO®, S-GOLD®,
SICAT®, SICOFI®, SIDEC®, SIEGET®, SLICOFI®, SMARTI®, SOCRATES®, VDSLite®, VINETIC®, 10BaseS® are
registered trademarks of Infineon Technologies AG.
ConverGate™, DIGITAPE™, DUALFALC™, EasyPort™, S-GOLDlite™, S-GOLD2™, S-GOLD3™, VINAX™,
WildPass™, 10BaseV™, 10BaseVX™ are trademarks of Infineon Technologies AG.
Microsoft® and Visio® are registered trademarks of Microsoft Corporation. Linux® is a registered trademark of
Linus Torvalds. FrameMaker® is a registered trademark of Adobe Systems Incorporated. APOXI® is a registered
trademark of Comneon GmbH & Co. OHG. PrimeCell®, RealView®, ARM® are registered trademarks of ARM
Limited. OakDSPCore®, TeakLite® DSP Core, OCEM® are registered trademarks of ParthusCeva Inc.
IndoorGPS™, GL-20000™, GL-LN-22™ are trademarks of Global Locate. ARM926EJ-S™, ADS™, Multi-ICE™
are trademarks of ARM Limited.
SLIC-E / TSLIC-E Subscriber Line Interface Circuit Enhanced Feature Set
Revision History: 2006-10-10, Revision 2.0
Previous Version: Revision 1.0
Page Subjects (major changes since last revision)
all Package P-/PG-VQFN-48-4 changed to PG-VQFN-48-15
all Package P-/PG-DSO-20-24 changed to PG-DSO-20-24
all Package P-/PG-DSO-36-10 changed to PG-DSO-36-15
Page 36 “Recommended PCB Foot Print Pattern for PG-VQFN-48-15 Package” on Page 36 modified.
Preliminary Data Sheet 4 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Version 2.1: Summary of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Current Limitation / Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Typical Application Circuit for DuSLIC® and VINETIC® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Foreign Line Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.1 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5.3.1 Frequency Dependence of PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Test Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 PG-DSO-20-24 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2 PG-VQFN-48-15 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.1 Recommended PCB Foot Print Pattern for PG-VQFN-48-15 Package . . . . . . . . . . . . . . . . . . . . . . 36
6.3 PG-DSO-36-15 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.1 Recommended PCB Foot Print Pattern for PG-DSO-36-15 Package . . . . . . . . . . . . . . . . . . . . . . . 38
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table of Contents
Preliminary Data Sheet 5 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Figure 1 Logic Symbol PEF 4265 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2 Logic Symbol PEF 4365 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3 Pin Configuration PG-DSO-20-24 Package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 Pin Configuration PG-VQFN-48-15 Package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5 Pin Configuration PG-DSO-36-15 Package (dual channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 Transversal and Longitudinal Line Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8 Application Circuit DuSLIC® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9 Application Circuit VINETIC® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 Typical Buffer Voltage Drop in Operating Modes ACTL, ACTH, ACTR . . . . . . . . . . . . . . . . . . . . . 27
Figure 11 Typical Frequency Dependence of PSRR VBATL/VTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12 Typical Frequency Dependence of PSRR VBATH/VTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13 Typical Frequency Dependence of PSRR VHR/VTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14 Typical Frequency Dependence of PSRR VDD/VTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15 Output Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16 Output Resistance PDRH, PDRHL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17 Current Outputs IT, IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19 Longitudinal to Transversal Rejection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20 Longitudinal to Transversal Rejection Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21 Transversal to Longitudinal Rejection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22 Ring Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23 Package Outline for PG-DSO-20-24 (Plastic Green Dual Small Outline). . . . . . . . . . . . . . . . . . . . 35
Figure 24 Package Outline for PG-VQFN-48-15 (Plastic Green Very thin Profile Quad Flatpack No-lead) . . 36
Figure 25 Package Outline for PG-DSO-36-15 (Plastic Green Dual Small Outline). . . . . . . . . . . . . . . . . . . . 37
Figure 26 Footprint for PG-DSO-36-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
List of Figures
Preliminary Data Sheet 6 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Table 1 Pin Definitions and Functions PG-DSO-20-24 and PG-VQFN-48-15 . . . . . . . . . . . . . . . . . . . . . . 12
Table 2 Pin Definitions and Functions PG-DSO-36-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3 SLIC-E Mode Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4 SLIC-E Modes and Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5 External Components DuSLIC® / VINETIC® for 2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7 Voltage Limits on Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8 Current Limits on Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10 Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11 Supply Currents, Power Dissipation (IR = IT = 0; VTR = 0; one channel) . . . . . . . . . . . . . . . . . . . . 23
Table 12 Output Stage Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13 DC Characteristics (VACP = VACN = 1.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of Tables
Preliminary Data Sheet 7 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
General Description
1 General Description
Infineon Technologies’ new high voltage ringing Subscriber Line Interface Circuit SLIC-E (PEF 4265 V2.1) is the
latest out of the well-known and broadly used SLIC-E family. It has been designed not only to cover all previous
SLIC-E applications, but also for particular “ADSL friendliness” and thus enables the realization of highly cost
optimized integrated voice data (IVD) systems. Special effort has been put on minimizing the influence of line
voltage transients and distortions caused by mode transitions and the associated unavoidable impedance
changes.
As SLIC-E V2.1 is pin compatible with its previous versions, it can be operated with all codec devices of the
DuSLIC® or VINETIC® chip sets. The highly flexible device offers 3.3 V compatibility and integrated balanced
ringing up to 85 Vrms. Integrated supply switches allow the choice between two negative battery voltages for voice
transmission, whereas in the ring mode an additional positive supply voltage is used.
To minimize the average system power dissipation, a power-down mode can be utilized; the transmission part is
switched off completely and off-hook supervision is provided by activating a simple line current sensor with
negligible power consumption.
SLIC-E V2.1 is available in a single (PEF 4265) channel version in either PG-DSO-20-24 or PG-VQFN-48-15
power packages, or in a dual channel version (PEF 4365), packaged in PG-DSO-36-15.
1.1 Version 2.1: Summary of Changes
Compared with the previous version of SLIC-E, PEF 4265 V1.2, the new version V2.1 is characterized by the
following changes:
• Improved high-frequency noise and distortion performance
• Optimized mode transitions to minimize influence on ADSL data in IVD systems
• Compatible with both 3.3 and 5 V VDD supplies
• High impedance DC inputs
• Fully differential receive path - VCMS pin not required
• Fast current limitation for improved overvoltage behaviour
• Application circuit:
– 100 nF / 50 V capacitor at CEXT
– Per channel series diode in VBATL supply mandatory (no shared diodes)
Version 2.1
Product Name Product Type Package
SLIC-E, SLIC-E2 PEF 4265 T, PEF 4265-2 T PG-DSO-20-24
SLIC-E, SLIC-E2 PEF 4265 V, PEF 4265-2 V PG-VQFN-48-15
TSLIC-E PEF 4365 T PG-DSO-36-15
P/PG-DSO-20-5
PG-DSO-20-24
PG-VQFN-48-15
PG-VQFN-48-15
P/PG-DSO-36-10
,
-12
,
-13
,
-14
,
-15
,
-1
6
PG-DSO-36-15
Preliminary Data Sheet 8 Revision 2.0, 2006-10-10
Subscriber Line Interface Circuit Enhanced Feature Set
SLIC-E
SLIC-E2
TSLIC-E
PEF 4265
PEF 4265-2
PEF 4365
1.2 Features
• “ADSL-friendly” high voltage SLIC with integrated ringing
• Compatible with both 3.3 and 5 V systems
• Available in single and dual-channel versions
• High-voltage line feed (long loop driving capability)
• Sensing of transversal and longitudinal line currents
• Two Battery voltages (–15 V … –85 V)
• Positive ring supply voltage up to +85 V
• Total supply voltage up to 150 V
• Integrated balanced ringing up to 85 Vrms
• High longitudinal balance performance with SLIC-E2 (PEF 4265-2)
• Power-saving active mode (ACTL) with reduced battery voltage
• Power Down mode with negligible power consumption
• Package options:
– PG-DSO-20-24
– PG-VQFN-48-15
– PG-DSO-36-15 (dual channel)
• Reliable Smart Power Technology (SPT170)
Preliminary Data Sheet 9 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
General Description
1.3 Logic Symbol
Figure 1 Logic Symbol PEF 4265
Figure 2 Logic Symbol PEF 4365
TIP
RING
VDD
AGND
VHR
BGND
VBATL
VBATH
CEXT
IT
IL
ACP
ACN
DCP
DCN
C1
C2
PEF 4265
Tip/Ring
interface
Power
supply
Logic
control
AC & DC
input
voltage
Scaled line
current
outputs
C3
PEF 4365
VDDA
AGNDA
VHRA
BGNDA
VBATH
Power
supply
channel A
VBATLA
TIPA
RINGA
Tip/Ring
interface
channel A ITA
ILA
Scaled line
current outputs
channel A
ACPA
ACNA
DCPA
DCNA
AC & DC
input voltage
channel A
C1A
C2A
Logic control
channel A
CEXTA
VDDB
AGNDB
VHRB
BGNDB
VBATH
Power
supply
channel B
VBATLB
TIPB
RINGB
Tip/Ring
interface
channel B ITB
ILB
Scaled line
current outputs
channel B
ACPB
ACNB
DCPB
DCNB
AC & DC
input voltage
channel B
C1B
C2B
Logic control
channel B
CEXTB
channel A
channel B
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
General Description
Preliminary Data Sheet 10 Revision 2.0, 2006-10-10
1.4 Pin Configuration
Figure 3 Pin Configuration PG-DSO-20-24 Package (top view)
Figure 4 Pin Configuration PG-VQFN-48-15 Package (top view)
VBATH
N.C.
AGNDACN
ACP
DCN
DCP
C3
C2
C1
IL
IT
N.C.
SLIC-E
PEF 4265 V2.1
PG-DSO-20-24
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
RING
TIP
BGND
VHR
VDD
VBATL
CEXT
Pin counting
is clockwise!
20
19
SLIC-E
PEF 4265 V2.1
PG-VQFN-48-15
24
23
22
21
20
19
18
17
16
15
14
13
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
12
11
10
9
8
7
6
5
4
3
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
2
1
CEXT
N.C. N.C.
RING
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AGND
N.C.
N.C.
VBATH
VBATL
VHR
N.C.
TIP
N.C.
VDD
BGND
N.C.
IT
IL
C1
C2
C3
DCP
DCN
ACP
ACN
N.C.
N.C.
Preliminary Data Sheet 11 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
General Description
Figure 5 Pin Configuration PG-DSO-36-15 Package (dual channel)
ILA
ILB
C1B
DCPB
C2B
ITB
C1A
C2A
DCPA
DCNA
ACPA
ACNA
N.C.
RINGA
TIPA
TIPB
BGNDB
VDDB
VHRB
RINGB
BGNDA
VHRA
VDDA
VBATLA
VBATH
AGNDA
CEXTA
ITA
VBATLB
VBATH
AGNDB
DCNB
ACPB
N.C.
ACNB
CEXTB
TSLIC-E
PEF 4365 V2.1
PG-DSO-36-15
13
1
5
9
11
3
7
10
8
6
4
2
14
12
17
15
16
18
23
32
27
29
25
30
28
26
24
34
31
33
35
36
19
21
22
20
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
General Description
Preliminary Data Sheet 12 Revision 2.0, 2006-10-10
1.5 Pin Definitions and Functions
Table 1 Pin Definitions and Functions PG-DSO-20-24 and PG-VQFN-48-15
Pin No.
DSO-20
Pin No.
VQFN-48
Name Pin
Type
Function
1 35 RING I/O Subscriber loop connection RING
2 38 TIP I/O Subscriber loop connection TIP
3 40 BGND GND Battery ground: reference for TIP, RING, VBATH, VBATL and VHR
4 41 VHR PWR Auxiliary positive battery supply voltage used in ringing mode
(5 V ≤VHR ≤ 85 V)
5 42 VDD PWR Positive supply voltage (+3.3 or +5 V), referred to AGND
6 43 VBATL PWR Second negative battery supply voltage (-15 V ≥VBATL ≥VBATH)
7 44 VBATH PWR Most negative battery supply voltage; chip substrate potential
(–20 V ≥VBATH ≥–85 V)
9 47 AGND GND Analog ground: reference for VDD and all signal and control pins
except TIP and RING
10 2 CEXT O Common mode line potential with high output resistance (160 kΩ); an
external capacitance allows supply voltage filtering
12
13
15
16
ACN
ACP
I ACP - ACN: differential two-wire AC input voltage; at TIP/RING
amplified by -6
14
15
17
18
DCN
DCP
I DCP - DCN: differential DC or ring input voltage; at TIP/RING
amplified by -30 (ACTL, ACTH) and -60 (ACTR mode), respectively
16 19 C3 I Ternary logic input, controlling the operation mode internal pull-down
(C3 = L, if not connected)
17 20 C2 I Ternary logic input, controlling the operation mode
18 21 C1 I/O Ternary logic input, controlling the operation mode in case of thermal
overload (chip temperature exceeding 165 °C) this pin sinks a current
of typically 150 µA.
19 22 IL O Current output: longitudinal line current scaled down by a factor of 100
20 23 IT O Current output: transversal line current scaled down by a factor of 50
8, 11 1)
1) For the PG-VQFN-48-15 package the following pins are not connected:
1,3,4,5,6,7,8,9,10,11,12,13,14,24,25,26,27,28,29,30,31,32,33,34,36,37,39,45,46,48
N.C. Not connected
Preliminary Data Sheet 13 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
General Description
Table 2 Pin Definitions and Functions PG-DSO-36-15
Pin No. Name Pin Type Function
1
10
RINGA
RINGB
I/O Subscriber loop connection RING (Channel A)
Subscriber loop connection RING (Channel B)
2
11
TIPA
TIPB
I/O Subscriber loop connection TIP
3
12
BGNDA
BGNDB
GND Battery ground: reference for TIP, RING, VBATH, VBATL and VHR
4
13
VHRA
VHRB
PWR Auxiliary positive battery supply voltage used in ringing mode
(5 V ≤VHR ≤ 85 V)
5
14
VDDA
VDDB
PWR Positive supply voltage (+3.3 or +5 V), referred to AGND
6
15
VBATLA
VBATLB
PWR Second negative battery supply voltage (–15 V ≥VBATL ≥VBATH)
7, 16 VBATH PWR Most negative battery supply voltage; chip substrate potential
(–20 V ≥VBATH ≥–85 V)
8
17
AGNDA
AGNDB
GND Analog ground: reference for VDD and all signal and control pins
except TIP and RING
9
18
CEXTA
CEXTB
O Common mode line potential with high output resistance (160 kΩ);
an external capacitance allows supply voltage filtering
29, 30
20, 21
ACNA, ACPA
ACNB, ACPB
I ACP - ACN: differential two-wire AC input voltage; at TIP/RING
amplified by -6
31, 32
22, 23
DCNA, DCPA
DCNB, DCPB
I DCP - DCN: differential DC or ring input voltage; at TIP/RING amplified
by -30 (ACTL, ACTH) and -60 (ACTR mode), respectively
33
24
C2A
C2B
I Ternary logic input, controlling the operation mode
34
25
C1A
C1B
I/O Ternary logic input, controlling the operation mode
in case of thermal overload (chip temperature exceeding 165 °C) this
pin sinks a current of typically 150 µA.
35
26
ILA
ILB
O Current output: longitudinal line current scaled down by a factor of 100
36
27
ITA
ITB
O Current output: transversal line current scaled down by a factor of 50
19, 28 N.C. Not connected
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
General Description
Preliminary Data Sheet 14 Revision 2.0, 2006-10-10
1.6 Functional Block Diagram
Figure 6 Block Diagram
Note: As in the dual channel version both channels “A” and “B” are identical, channel independent pin names (e.g.
“TIP” instead of “TIPA / TIPB”) are used throughout this document (with the exception of Table 2)
TIP
RING
I
R
Mode
Control
Current
Sensor
C1
VBATL
SLIC-E V2.1
Off-hook
VDD
VBI
VBATH
C3
IT
IL
(I
T0
+ I
R0
)/10
5k
BGND
PDRH
PDRH
AGND
C2
(I
T
+ I
R
)/100
(I
T
- I
R
)/200
I
T0
I
R0
VBAT
Switch
R/6
R/30
R/6
R/30
R
VCM
ACN
DCN
DCP
ACP
VBI
VHI
VHI
CEXT
*1 (*2)
*1 (*2)
5k
VH
switch
VHI
VHR
BGND
V
DOH
-
+
+
+
+
-
-
-
I
T
R
Bias
Preliminary Data Sheet 15 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Functional Description
2 Functional Description
A functional block diagram is shown in Figure 6.
SLIC-E V2.1 supports AC and DC control loops based on feeding a voltage VTR to the line and sensing the
transversal line current ITrans and the longitudinal current ILong.
In receive direction, DC and AC voltages are handled separately with different gains. Both are applied differentially
via the codec interface pins DCP / DCN and ACP / ACN, respectively, defining the transversal line voltage VTR
through
VTR = VTIP – VRING = Vab =
= 30 * (VDCP – VDCN) + 6 * (VACP – VACN) for modes ACTH, ACTL
= 60 * (VDCP – VDCN) + 6 * (VACP – VACN) for mode ACTR
As the ring signal is processed in the DC path, the DC gain is doubled in the ring mode ACTR to enable the full
output voltage swing.
The common mode line voltage is always equal to the mean supply voltage, VCM = (VHI + VBI) / 2, leading to
symmetrical line potentials with respect to the supplies. Depending on the operation mode, VHI is switched either
to VHR or to BGND via the VH switch, whereas VBI is connected either to VBATH via the VBAT switch or to VBATL via
an external diode.
A reversed polarity of VTR is easily obtained by changing the polarity of (VDCP – VDCN).
In transmit direction, the transversal and longitudinal line currents ITrans and ILong (Figure 7) are measured, and
scaled images are provided at the IT and IL pins, respectively:
For off-hook detection in PDRH mode, 5 kΩ resistors are connected from TIP to BGND and from RING to VBATH,
respectively. The currents through these resistors, IT0 and IR0, are sensed, scaled and provided at IT:
IIT0 = (IT0 + IR0) / 10 = ITRANS0 / 5
Figure 7 Transversal and Longitudinal Line Currents
IIT = (IT+IR) / 100 = ITrans / 50 IIL =(IT–IR) / 200 = ILong / 100
ITrans = (IT+IR) / 2 ILong =(IT–IR) / 2
V
TR
Z
L
/2
RING
TIP
I
Long
Z
L
/2
V
TIP
V
RING
I
Trans
I
R
V
Long
I
T
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Functional Description
Preliminary Data Sheet 16 Revision 2.0, 2006-10-10
2.1 Operating Modes
SLIC-E V2.1 operates in the following modes controlled by ternary logic signals at C1, C2 and a binary signal at
C3 (PEF 4265 only)
Power Down High Impedance (PDH)
PDH offers high impedance at TIP and RING; it can be used for testing purposes or when an error condition
occurs. In PDH mode all functions are switched off. Off-hook detection is not available.
Power Down Resistive High (PDRH)
Power consumption is reduced to a minimum by switching completely off all voice transmission functions. To allow
off-hook detection, PDRH provides a connection of 5 kΩ each from TIP to BGND and RING to VBATH,
respectively, while the output buffers show high impedance (see Figure 6). The current through these resistors is
sensed, scaled by 1/5 and transferred to the IT pin for off-hook supervision.
Power Down Resistive High Load (PDRHL)
PDRHL is used as a transition state from Power Down to Active modes (automatically initiated during a mode
change). It causes fast preloading of CEXT in order to suppress line voltage transients.
Table 3 SLIC-E Mode Table
C2
LMH
C1 L1)
1) No ‘Overtemp’ signaling possible via pin C1 if C1 is low.
PDH PDRHL PDRH L or N.C.2)
2) Register setting (VINETIC®): SEL-SLIC = (0001)hex
C33)
3) Not connected in dual-channel version PEF 4365
HIRT H4)
4) Register setting (VINETIC®): SEL-SLIC = (0100)hex
MACTL ACTH ACTR L or N.C.2)
H4)
HHIRT HIT HIR L or N.C.2)
ACTH-R H4)
Table 4 SLIC-E Modes and Supplies
Mode Mode Description Internal Supply Voltages VBI, VHI
PDH Power Down High Impedance VBATH, VH switch open
PDRH Power Down Resistive High VBATH, VH switch open
PDRHL Power Down Resistive High Load VBATH, VH switch open
ACTL Active Low VBATL, BGND
ACTH Active High VBATH, BGND
ACTH-R Active High Resistive VBATH, BGND
ACTR Active Ring VBATH, VHR
HIRT High Impedance on RING and TIP VBATH, VHR
HIT High Impedance on TIP VBATH, VHR
HIR High Impedance on RING VBATH, VHR
Preliminary Data Sheet 17 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Functional Description
Active Low (ACTL), Active High (ACTH)
These are the regular transmission modes for voiceband. The line-driving section is operated between BGND and
VBATL (ACTL) or VBATH (ACTH).
Active High Resistive (ACTH-R)
The SLIC is operated in Active High state together with the 5 kΩ resistors from TIP to BGND and from RING to
VBATH. This mode is intended to be used for line testing.
Active Ring (ACTR)
Utilizing an additional positive battery voltage VHR, this mode allows balanced ringing of up to 85 Vrms or feeding
of very long telephone lines. In ACTR mode the DC voltage gain is doubled to 60.
High Impedance (HIR, HIT, HIRT)
In these modes each of the line outputs can be programmed to show high impedance. HIT switches off the TIP
buffer, while HIR switches off the RING buffer. The current through the active buffer is still sensed. In the HIRT
mode both buffers show high impedance. The current sensor remains active thus allowing sensor offset calibration
(for test purposes).
2.2 Current Limitation / Overtemperature Protection
In any operating mode the total current delivered by the output drivers is limited to typically 85 mA.
If, however, the junction temperature exceeds 165 °C, the current limit is further reduced to keep the junction
temperature constant.
Simultaneously, pin C1 sinks a signalling current Itherm.
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Typical Application Circuit for DuSLIC® and VINETIC®
Preliminary Data Sheet 18 Revision 2.0, 2006-10-10
3 Typical Application Circuit for DuSLIC® and VINETIC®
Figure 8 to Figure 9 show one channel of application circuits including SLIC-E / TSLIC-E V2.1 and SLICOFI®-2/-
2S or VINETIC® codec (please refer to the latest DuSLIC® or VINETIC® Data Sheet).
In Table 5 the recommended external components for a dual channel DuSLIC® or VINETIC® system and their
typical values are listed.
The C3 pin of SLIC-E V2.1 can be either
• Not connected (or connected to AGND) to be compatible with previous SLIC-E/-E2 versions or
• Connected to IO0x (IO2x) of VINETIC® (SLICOFI®-2/-2S) to offer an additional test mode ACTH-R.
Table 5 External Components DuSLIC® / VINETIC® for 2 Channels
No. Symbol Value Unit Relat. Tol. Rating DuSLIC®
Systems
VINETIC®
Systems
2RIT1 470 Ω1% – x –
2RIT1 510 Ω1% – – x
2RIT2 680 Ω1% – x x
2RIL 1.6 kΩ1% – x x
4RSTAB 30 Ω1%
1)
1) Matching tolerance depends on longitudinal balance requirements (for details see [2]).
–xx
4CSTAB 15 (POTS)
22 (IVD)
nF
nF
10 %
10 %
100 V
100 V
x
x
x
x
2CDC 120 nF 10 % 10 V x –
2CDC 220 nF 10 % 10 V – x2)
2) With VINETIC®-2CPE this capacitance is substituted by 100 nF between DCN and DCP.
2CITAC 680 nF 10 % 10 V x –
2CITAC 1µF10% 10V – x
1CPRE 18 nF 5 % 10 V – x
2CVCMIT 680 nF 10 % 10 V x –
1CREF 68 nF 20 % 10 V x x
2CEXT 100 nF 20 % 50 V x x
6C1100 nF 10 % 10 V x –
13 C1100 nF 10 % 10 V – x
6C2100 nF 10 % 100 V x x
1C34.7 µF 20 % 10 V, Tantal x –
4D1, D2BAS 21 – – – x x
2D3
3)
3) Due to the changed battery switch concept (see Figure 6), the VBATL series diode must not be shared between different
channels; one diode per channel is mandatory (also for applications with TSLIC).
BAS 21 – – – x x
2OVP
4)
4) See [1]
Overvoltage Protection
(e.g. thyristor)
–– – x x
4OCP
4) Overcurrent Protection
(e.g. LFR, fuse, PTC)
–– – x x
Preliminary Data Sheet 19 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Typical Application Circuit for DuSLIC® and VINETIC®
Figure 8 Application Circuit DuSLIC®
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
CDCPA
ITACA
ITA
VCMITA
ILA
VCM
VCMS
C
DC
SLICOFI-2
C
ITACA
R
IT1A
R
IT2A
R
ILA
ACP
ACN
DCP
DCN
C1
C2
IL
IT
BGND AGND CEXT
C
EXT
RING
TIP
Channel A
PEF 4265 V2.1
OVPOVP
C
STAB
BGND
C
STAB
IO0A ... IO4A 5
GPIO0 ... GPIO7 8
CREFAB
GNDAB
GNDA GND GNDP
C
REF
PCM / µC
Interface
IOM-2
Interface
C3 N.C. or IO2x
OCP
Overvoltage protection
C
VCMITA
OCP
V
DDA
V
DDR
V
DDD
V
DDPLL
C
1
C
1
C
1
C
1
V
DD33
C
3
SLIC-E
R
STAB
R
STAB
V
HR
V
DD
V
BATH
V
BATL
V
BATL
V
BATH
V
DD
V
HR
D
3
D
1
D
2
C
2
C
2
C
2
C
1
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Typical Application Circuit for DuSLIC® and VINETIC®
Preliminary Data Sheet 20 Revision 2.0, 2006-10-10
Figure 9 Application Circuit VINETIC®
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
CDCPA
ITACA
ITA
VCMITA
ILA
VCMAB
VREFAB
VINETIC-x
R
IT1A
SLIC-E
R
IT2A
R
ILA
ACP
ACN
DCP
DCN
C1
C2
IL
IT
BGND AGND CEXT
RING
TIP
Channel A
PEF 4265 V2.1
OVP
OVP
C
STAB
BGND
C
STAB
IO0A ... IO4A 5
GPIO0 ... GPIO7 8
CREFAB
GNDAB
GNDA GND GNDP
V
HR
V
DD
V
BATH
V
BATL
V
BATL
V
BATH
V
DD
V
HR
D
3
D
1
D
2
PCM / µC
Interface
Parallel
Interface
C3 N.C. or IO0x
OCP
Overvoltage protection
C
ITACA
C
PRE
C
DC
C
REF
OCP
V
DD18x
......
C
1
C
1
C
1
C
1
V
DD18
V
DD33x
......
V
DD33
C
2
C
2
C
2
C
1
R
STAB
R
STAB
Preliminary Data Sheet 21 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
Attention: Stresses exceeding the max. values listed above may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
4.2 Foreign Line Voltages
External voltages applied at the line outputs may cause large currents in the SLIC. The resulting on-chip power
dissipation has to be limited to avoid thermal destruction, if the overtemperature protection cannot react sufficiently
fast due to high local power density. The safe power dissipation values are strongly dependent on duration. They
can be expressed in terms of voltage and current limits directly at the TIP and RING pins (see Table 7 and
Table 8).
Table 6 Absolute Maximum Ratings
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Battery voltage low VBATL –85 – 0.4 V Referred to BGND
Battery voltage high VBATH –90 – 0.4 V Referred to BGND
Battery voltage difference VBATL –VBATH –0.4 – – V –
Auxiliary supply voltage VHR –0.4 – 90 V Referred to BGND
Total battery supply
voltage, continuous
VHR –VBATH –0.4 – 160 V –
VDD supply voltage VDD –0.4 – 7 V Referred to AGND
Ground voltage difference VBGND –VAGND –0.4 – 0.4 V –
Input voltages VDCP, VDCN,
VACP, VACN,
VC1, VC2, VC3
–0.4 – VDD + 0.4 V Referred to AGND
Junction temperature Tj––150°C–
ESD voltage, all pins – – – 1 kV SDM (Socketed Device Model)1)
1) EOS/ESD Assn. Standard DS5.3-1993.
– – – 1 kV HBM (Human Body Model)1)
Table 7 Voltage Limits on Output Pins
Voltage Duration Pins Min. Voltage [V] Max. Voltage [V]
Continuous TIP, RING VBATH – 0.4 VHR + 5
< 10 ms TIP, RING VBATH – 5 VHR + 10
< 100 µsTIP, RING
VBATH – 10 VHR + 20
< 1 µsTIP, RING
VBATH – 15 VHR + 40
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
Preliminary Data Sheet 22 Revision 2.0, 2006-10-10
The above limitations have to be regarded as typical. They are valid simultaneously. Together with external
circuitry they determine protection requirements (see [1]).
4.3 Operating Range
4.4 Thermal Resistances
Table 8 Current Limits on Output Pins
Current Duration Pins Min. current [A] Max. current [A]
Continuous TIP, RING – 0.1 0.1
< 10 ms TIP, RING – 0.5 0.5
< 100 µs TIP, RING – 1.0 1.0
< 1 µs TIP, RING – 1.5 1.5
Table 9 Operating Range
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Battery voltage L1)
1) If the battery switch is not used, VBATL has to be connected with VBATH
VBATL –80 – –15 V Referred to BGND
Battery voltage H 1) VBATH –85 – –20 V Referred to BGND
Auxiliary supply voltage VHR VDD – 85 V Referred to BGND
Total battery supply voltage VHR –VBATH ––150V–
VDD supply voltage VDD 3.15 – 5.5 V Referred to AGND
Ground voltage difference VBGND –V
AGND –0.4 – 0.4 V –
Voltage at pins IT, IL VIT, VIL –0.4 – VDD - 0.6 V Referred to AGND
Input range VDCP, VDCN, VACP, VACN 0 – 3.3 V Referred to AGND
Ambient temperature Tamb –40 – 85 °C–
Junction temperature TJ––125
2)
2) Operation up to TJ= 150 °C possible. However, a permanent junction temperature exceeding 125 °C could degrade device
reliability.
°C–
Table 10 Thermal Resistances
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Junction to case Rth, jC – 2 – K/W All packages
Junction to ambient Rth, jA – 50 – K/W PG-DSO-20-24 without heatsink
– 20 – K/W PG-DSO-20-24 with heatsink
PG-DSO-36-15, 4-layer JEDEC PCB with vias, die
pad soldered to PCB (footprint see Chapter 6.3.1)
Junction to ambient Rth, jA – 25 – K/W PG-VQFN-48-15, 4-layer JEDEC PCB with vias, die
pad soldered to PCB (footprint see Chapter 6.2.1)
Preliminary Data Sheet 23 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
4.5 Electrical Parameters
Unless otherwise stated, minimum and maximum values are valid within the full operating range.
Testing is performed according to the specific test figures at VBATH = –48 V, VBATL =–24V, VHR = +32 V and
VDD =+3.3V.
Functionality and performance is guaranteed for TA= 0 to 70 °C by production testing. Extended temperature
range operation at –40 °C < TA< 85 °C is guaranteed by design, characterization and periodically sampling and
testing production devices at the temperature extremes.
4.5.1 Supply Currents and Power Dissipation
Table 11 Supply Currents, Power Dissipation (IR = IT = 0; VTR = 0; one channel)
Parameter Symbol Values Unit Note /
Test Condition
No.
Min. Typ. Max.
Power Down High Impedance, Power Down Resistive High
VDD current IDD – 250 350 µA– 1
VBATH current IBATH –4080µA– 2
VBATL current IBATL –010µA– 3
VHR current IHR –010µA– 4
Active Low
VDD current IDD –2.22.8mA– 5
VBATH current IBATH –4080µA– 6
VBATL current1) IBATL –3.34 mA– 7
VHR current IHR –010µA– 8
Active High
VDD current IDD –2.63.2mA– 9
VBATH current2) IBATH – 3.8 4.5 mA – 10
VBATL current IBATL –010µA– 11
VHR current IHR –010µA– 12
Active Ring
VDD current IDD –1.52 mA– 13
VBATH current3) IBATH – 3.5 4.3 mA – 14
VBATL current IBATL –010µA– 15
VHR current4) IHR – 1.8 2.3 mA – 16
High Impedance on TIP or RING (HIR, HIT)
VDD current IDD –1.52 mA– 17
VBATH current IBATH – 2.9 3.6 mA – 18
VBATL current IBATL –010µA– 19
VHR current IHR – 1.3 1.7 mA – 20
High Impedance on TIP and RING (HIRT)
VDD current IDD – 1.4 1.8 mA – 21
VBATH current IBATH 2.2 2.8 mA – 22
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
Preliminary Data Sheet 24 Revision 2.0, 2006-10-10
The total power dissipated in the SLIC consists of the quiescent power PQ due to the supply currents and the
output stage power PO caused by any line current ITrans (see Table 12).
Ptot = PQ + PO
with PQ = VDD * IDD + IVBATHI * IBATH + IVBATLI * IBATL + VHR * IHR
For the dual channel version, the power values of each channel have to be added to yield the total power
dissipation.
VBATL current IBATL –010µA– 23
VHR current IHR – 0.8 1.1 mA – 24
1) Current depending on supply voltage: IBATL (VBATL) =
Ι
BATL (-24V) + (-VBATL - 24) / 40kΩ
2) Current depending on supply voltage: IBATH (VBATH) = IBATH (-48V) + (-VBATH - 48) / 40kΩ
3) Current depending on line voltage: IBATH (VTR) = IBATH (0) + |VTR| / 40kΩ
4) Current depending on line voltage: IHR (VTR) = IHR (0) + |VTR| / 60kΩ
Table 12 Output Stage Power Dissipation
Operating Mode Equation for PO Calculation Comment
ACTL PO = (1.05 * |VBATL| – VTR)*ITrans –
ACTH PO = (1.05 * |VBATH| – VTR)*ITrans –
ACTR PO = (1.02 * VHR + 1.05 * |VBATH| – VTR)*ITrans
PO = [4 * (VH + |VBATH|) - π*VP*cos ϕ]*VP / (2 * π*ZL)
Ohmic load
complex load Z = ZLeiϕ,
VP ... peak ring voltage
Table 11 Supply Currents, Power Dissipation (IR = IT = 0; VTR = 0; one channel) (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
No.
Min. Typ. Max.
Preliminary Data Sheet 25 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
4.5.2 DC Characteristics
Table 13 DC Characteristics (VACP = VACN = 1.5 V)
Parameter Symbol Values Unit Note / Test Condition No.
Min. Typ. Max.
Line Termination TIP, RING
Differential DC line voltage VTR, DC –0.4 0 0.4 V VDCP = VDCN = 1.5 V
Modes: ACTx
25
23.5 24 24.5 V VDCP – VDCN = 0.8 V
Mode: ACTH
26
–24.5 –24 –23.5 V VDCP – VDCN = –0.8 V
Mode: ACTH
27
Common mode DC line VTIP, DC = –13 –12 –11 V Mode: ACTL 28
voltage = VRING, DC –25 –24 –23 V Mode: ACTH 29
–10 –9 –8 V Mode: ACTR 30
DC line voltage drop
(see Figure 10)
– VBATH –
VTR, max
–2.53VITrans,DC = 20 mA
VDCP – VDCN = 2.5 V
Temp = 25°C1)
Mode: ACTH
31
Output current limit (see
Figure 15)
|IR, max|, |IT, max|70 85 100 mAVT,VR = 0 (sinking)
VT,VR = VBATx
(sourcing)
Temp = 25°C2)
32
80 100 120 mA 33
Open loop resistance TIP
to VBGND (see Figure 16)
RTG 4.2 5 5.8 kΩTemp = 25°C3)
Mode: PDRH
34
Open loop resistance
RING to VBATH (see
Figure 16)
RRB 4.2 5 5.8 kΩTemp = 25°C3)
Mode: PDRH
35
Power down open loop line
voltage
VTR,PD =
= – VBATH – VDOH
42 44 47 V Mode: PDRH 36
Power down
output leakage current
ILeak,R –10 – 10 µAVBATH < VT/R < 0 37
ILeak,T –10 – 10 µA Mode: PDH 38
High impedance
output leakage current
ILeak,R –10 – 10 µAVBATH < VR < VHR
Mode: HIR, HIRT
39
ILeak,T –10 – 10 µAVBATH < VT < VHR
Mode: HIT, HIRT
40
Inputs DCP, DCN, ACP, ACN, Output CEXT
Input current DCP, DCN IDC –0.1–µA– 41
Differential AC input
resistance ACP, ACN
RAC –20–kΩ–42
Output resistance on CEXT ––100–kΩ–43
Current Outputs IT, IL
IT output current IIT –15 0 15 µAIR = IT = 0 mA 44
IT output current normal
polarity
IIT 380 400 420 µAIR = IT = 20 mA 45
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
Preliminary Data Sheet 26 Revision 2.0, 2006-10-10
IT output current reverse
polarity4)
IIT –420 –400 –380 µAIR = IT = –20 mA 46
Transversal current ratio
(see Figure 18)5)
1/GIT,DC 49.5 50 50.5 – IR = IT = 20 mA,
IR = IT = –20 mA
47
Off-hook output current on
IT
– 800 950 1100 µA TIP/RING shorted,
Temp = 25 °C6)
Mode: PDRH
48
IL output current
(see Figure 18)
IIL –20 0 20 µAIR = IT = 20 mA 49
30 50 70 µAIR = 15 mA, IT = 25 mA 50
–160 –125 –90 µAIR = 50 mA, IT = 25 mA 51
Control Inputs C1, C2, C3
H-input voltage VIH 2.7 – VDD +
0.3
V– 52
M-input voltage VIM 1.2 – 2.1 V C1, C2 only 53
L-input voltage VIL –0.3 – 0.6 V – 54
Input pull down current Iin 0210µA C1, C2, C3 55
Thermal overload current
C1
Itherm 120 150 250 µAVC1 = 1.20 V 56
Thermal overload
threshold temperature
TjLIM – 165 – °C Mode: ACTx, HIx 57
1) The systematic temperature dependence is appr. + 7 mV / °C
2) The systematic temperature dependence is appr. -0.3 % / °C
3) The systematic temperature dependence is appr. +0.1 %/ °C
4) With VDD = 3.3 V, the IT output current in reverse polarity is limited to typically 700 µA; thus, the DC current regulation
loop operates correctly only up to the corresponding line current value of 35 mA. In all other cases, IT is linear within the
full line current range
5) The offset (IR = IT = 0 mA) has to be taken into account.
6) The systematic temperature dependence is appr. -0.1 %/ °C
Table 13 DC Characteristics (VACP = VACN = 1.5 V) (cont’d)
Parameter Symbol Values Unit Note / Test Condition No.
Min. Typ. Max.
Preliminary Data Sheet 27 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
Figure 10 Typical Buffer Voltage Drop in Operating Modes ACTL, ACTH, ACTR
4.5.3 AC Characteristics
If not otherwise stated, AC characteristics are tested at a DC line current of 25 mA and –25 mA, respectively; they
are valid in all active modes.
Table 14 AC Characteristics
Parameter Symbol Values Unit Note / Test Condition No.
Min. Typ. Max.
Line Termination TIP, RING
Receive gain (see Figure 18)Gr5.925 6.0 6.075 – VACP – VACN = 640 mVrms,
f = 1015 Hz
58
Total harmonic distortion VTR
(see Figure 18)
THD –0.01–%VACP – VACN = 640 mVrms,
f = 1015 Hz
59
Teletax distortion THDTTX –0.1–%VTR,AC = 5 Vrms, f = 16 kHz,
RL = 200 Ω
60
–0.2–%
VTR,AC = 5 Vrms, f = 16 kHz,
RL = 200 Ω, ITrans,DC = 0 mA
61
Psophometric noise
(see Figure 18 )
NpVTR – –82 –78 dBmp – 62
Longitudinal to transversal
rejection ratio Vlong/VTR
(see Figure 19)
LTRR –80–dBVlong = 3 Vrms,
300 Hz < f < 3.4 kHz
63
Longitudinal to transversal
rejection ratio Vlong/VTR (loop)
PEF 4265, PEF 4365
(see Figure 19)
LTRRloop
54 58 – dB
Vlong = 3 Vrms
300 Hz < f < 1kHz 64
52 56 – dB f = 3.4 kHz 65
0
1
2
3
4
5
6
7
8
9
0 102030405060
ACTR
ACTH, ACTL
I
trans
[mA]
V
drop
[V]
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
Preliminary Data Sheet 28 Revision 2.0, 2006-10-10
Longitudinal to transversal
rejection ratio Vlong/VTR (loop)
PEF 4265-2
(see Figure 19)
LTRR-2loop
61 65 – dB
Vlong = 3 Vrms
300 Hz < f < 1kHz 66
56 60 – dB f = 3.4 kHz 67
Transversal to longitudinal
rejection ratio VTR/Vlong(see
Figure 21)
TLRR 48 60 – dB VACP – VACN = 1920 mVrms,
300 Hz < f < 3.4 kHz
68
Power supply rejection ratio
(see Figure 11, Figure 12,
Figure 14, Figure 14)
PSRR VSupplyAC = 100 mVp,
300 Hz < f < 3.4 kHz
69
VBATL/VTR 40 60 – dB
VBATH/VTR 40 60 – dB 70
VHR/VTR 33 50 – dB 71
VDD/VTR 33 50 – dB 72
Interchannel crosstalk1) -80 – dB 300 Hz < f < 3.4 kHz
both channels active
73
-80 – dB One channel active,
one channel power down
74
Ringing amplitude TIP/RING VRNG0 –85–VrmsVDCP – VDCN = 0.15 V (DC)
+ 1.42 Vrms (sine wave,
20Hz)
RR = 450 Ω, CR = 3.4 µF,
Mode: ACTR
75
Ringing distortion (see
Figure 22)
RD – 0.1 – % 76
Transversal Current IT2)
Transversal current ratio
(see Figure 18)
1/Git VACP – VACN = 640 mVrms,
f = 1015 Hz
7749.5 50 50.5 ITrans,DC = 25 mA
49 50 51 ITrans,DC = –25 mA 78
Total harmonic distortion VIT THDIT – 0.02 0.3 % VACP – VACN = 640 mVrms,
f = 1015 Hz
79
Psophometric noise
(see Figure 18)
NpVIT – –110 –105 dBmp – 80
Longitudinal to transversal
current output rejection ratio
Vlong/VIT (see Figure 19)
LITRR –85–dBVlong = 3 Vrms,
300 Hz < f < 3.4 kHz
81
Power supply rejection ratio PSRR VSupplyAC = 100 mVp,
300 Hz < f < 3.4 kHz 82
VBATL/VIT 50 70 – dB
VBATH/VIT 50 70 – dB 83
VHR/VIT 50 70 – dB 84
VDD/VIT 50 70 – dB 85
1) Dual channel version PEF 4365 only
2) Unless otherwise specified, characteristics are valid for both DC line current directions (normal and reverse polarity)
Table 14 AC Characteristics (cont’d)
Parameter Symbol Values Unit Note / Test Condition No.
Min. Typ. Max.
Preliminary Data Sheet 29 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
4.5.3.1 Frequency Dependence of PSRR
Figure 11 Typical Frequency Dependence of PSRR VBATL/VTR
Figure 12 Typical Frequency Dependence of PSRR VBATH/VTR
PSRR V
BATL
/ V
TR
0
10
20
30
40
50
60
70 0.1 1 10 100 1000
Frequency [kHz]
V
BATL
/ V
TR
[dB]
0
10
20
30
40
50
60
70 0.1 1 10 100 1000
Frequency [kHz]
V
BA T H
/ V
TR
[dB]
PSRR V
BATH
/ V
TR
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Electrical Characteristics
Preliminary Data Sheet 30 Revision 2.0, 2006-10-10
Figure 13 Typical Frequency Dependence of PSRR VHR/VTR
Figure 14 Typical Frequency Dependence of PSRR VDD/VTR
0
10
20
30
40
50
60
70 0.1 1 10 100 1000
Frequency [kHz]
V
HR
/ V
TR
[dB]
PSRR V
HR
/ V
TR
0
10
20
30
40
50
60
70 0.1 110
100 1000
Frequency [kHz]
ACTL, ACTH
ACTR
V
DD
/ V
TR
[dB]
PSRR V
DD
/ V
TR
Preliminary Data Sheet 31 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Test Figures
5 Test Figures
Figure 15 Output Current Limit
Figure 16 Output Resistance PDRH, PDRHL
V
T
or V
R
connected to:
BGND, VBATH (ACTH)
BGND, VBATL (ACTL)
VHR, VBATH (ACTR)
PEF 4265 V2.1
TIP
RING
IT
CEXT
ACP
C1 VHR
VBATL BGND
DCP
DCN
ACN
IL
AGND
VDD
30 Ω
=
~
V
DC
= 0
V
AC
= 0
+32 V+5 V
-48 V
I
T,max
I
R,max
C3VBATH
=1.5 V
-24 V
1.6 kΩ
30 Ω
1 kΩ
V
T
V
R
100 nF
15 nF
15 nF
C2
PEF 4265 V2.1
TIP
RING
IT
CEXT
ACP
C1 VHRVBATL BGND
DCP
DCN
ACN
IL
AGND
VDD
=
~
V
DC
= 0
V
AC
= 0
+32 V
+5 V-48 V
C3VBATH
=1.5 V
-24 V
1.6 kΩ
1 kΩ
100 nF
C2
VBATH
VBATH
2 mA
2 mA
30 Ω
30 Ω
15 nF
15 nF
R
TG
= V
T
/ 2 mA
R
RB
= V
R
/ 2 mA
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Test Figures
Preliminary Data Sheet 32 Revision 2.0, 2006-10-10
Figure 17 Current Outputs IT, IL
Figure 18 Transmission Characteristics
PEF 4265 V2.1
C1 VHRVBATL BGNDAGND
VDD
+32 V+5 V-48 V
C3VBATH
-24 V
C2
IT
CEXT
ACP
DCP
DCN
ACN
IL
=
~
=
1 kΩ
V
DC
= 0
1.5 V
100 nF
V
AC
= 0
V
IL
V
IT
1.6 kΩ
TIP
RING
I
T
I
R
30 Ω
30 Ω
15 nF
15 nF
I
IT
= -V
IT
/ 1 kΩ
I
IL
= -V
IL
/ 2 k Ω
PEF 4265 V2.1
C1 VHRVBATL BGNDAGND
VDD
+32 V+5 V-48 V
C3VBATH
-24 V
C2
IT
CEXT
ACP
DCP
DCN
ACN
IL
=
~
=
1 kΩ
1.5 V
100 nF
V
AC
= 0
V
IT
1.6 kΩ
TIP
RING
R
L
= 600 ΩV
TR , A C
30 Ω
30 Ω
15 nF
15 nF
G
r
= V
TR,AC
/ V
AC
G
IT
= - (V
IT,AC
/ 1000) / (V
TR,AC
/ 660)
V
DC
= I
TR
* 660 / 30
Preliminary Data Sheet 33 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Test Figures
Figure 19 Longitudinal to Transversal Rejection
Figure 20 Longitudinal to Transversal Rejection Loop
PEF 4265 V2.1
C1 VHRVBATL BGNDAGND
VDD
+32 V+5 V-48 V
C3VBATH
-24 V
C2
IT
CEXT
ACP
DCP
DCN
ACN
IL
=
~
=
1 kΩ
1.5 V
100 nF
V
AC
= 0
V
IT
1.6 kΩ
V
DC
= I
TR
* 660 / 30
LTRR = V
long
/ V
TR,AC
TIP
RING
V
TR, AC
~
V
long
30 Ω
30 Ω
300 Ω
300 Ω
15 nF
15 nF
LITRR = V
long
/ V
IT
PEF 4265 V2.1
C1 VHRVBATL BGND
AGND
VDD
+32 V+5 V-48 V
C3VBATH
-24 V
C2
IT
CEXT
ACP
DCP
DCN
ACN
IL
=
=
1 kΩ
1.5 V
100 nF
1.6 kΩ
V
DC
= I
TR
* 660 / 30
TIP
RING
V
TR, AC
~
V
long
30 Ω
30 Ω
300 Ω
300 Ω
15 nF
15 nF
G
loop
V
ACP - ACN
= G
loop
* V
IT,AC
LTRR
loop
= V
long
/ V
TR,AC
G
loop
= 4.5
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Test Figures
Preliminary Data Sheet 34 Revision 2.0, 2006-10-10
Figure 21 Transversal to Longitudinal Rejection
Figure 22 Ring Amplitude
PEF 4265 V2.1
C1 VHRVBATL BGND
AGND
VDD
+32 V+5 V-48 V
C3VBATH
-24 V
C2
IT
CEXT
ACP
DCP
DCN
ACN
IL
=
~
=
1 kΩ
1.5 V
100 nF
V
AC
= 1.92 V
rms
1.6 kΩ
V
DC
= I
TR
* 660 / 30
TIP
RING
V
TR
30 Ω
30 Ω
300 Ω
300 Ω
15 nF
15 nF
TLRR = VTR / Vlong
V
long
PEF 4265 V2.1
TIP
RING
IT
CEXT
ACP
C1 VHRVBATL BGND
DCP
DCN
ACN
IL
AGND
VDD
=
~V
AC
= 0
+32 V+5 V-48 V
C3VBATH
=1.5 V
-24 V
1.6 kΩ
1 kΩ
100 nF
C2
V
DC
= 0.15 V + 1.42 V
rms
V
RNG
3.4 µF
30 Ω
30 Ω
450 Ω15 nF
15 nF
Preliminary Data Sheet 35 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Package Outlines
6 Package Outlines
6.1 PG-DSO-20-24 Package
Figure 23 Package Outline for PG-DSO-20-24 (Plastic Green Dual Small Outline)
Notes
1. Heatsink on top - pin counting clockwise (top view)
2. Dimensions in mm
Attention: The heatsink is connected to VBATH via the chip substrate. Due to the high voltage of up to
150 V between VHR and VBATH, touching of the heatsink or any attached conducting part can
be hazardous.
GPS05755
(Metal)
Index Marking
2020 11
1 x 45˚
110
Heatslug
Bottom View
(Metal)
(Metal)
1
-0.3
1.2 2.8
3.55 MAX.
1.3
(Mold)
6.3
10
11
1) Does not include plastic or metal protrusion of 0.15 max. per side
+0.13
0.4
1.27
0.25 MA20x
±0.05
0.3
3.25
±0.1
0.1
±0.15
11 1)
B
0.25
-0.02
+0.07
±3˚
5˚
±0.15
0.95
14.2±0.3 0.25 B
±0.1
3.2
5.9
±0.1
-0.2
13.7
1)
±0.15
15.9 A
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Package Outlines
Preliminary Data Sheet 36 Revision 2.0, 2006-10-10
6.2 PG-VQFN-48-15 Package
Figure 24 Package Outline for PG-VQFN-48-15 (Plastic Green Very thin Profile Quad Flatpack No-lead)
Note: Dimensions in mm
Attention: The exposed die pad and the die pad edges are connected to VBATH via the chip substrate. Due
to the high voltage of up to 150 V between VHR and VBATH, touching of the die pad or any
attached conducting part can be hazardous.
6.2.1 Recommended PCB Foot Print Pattern for PG-VQFN-48-15 Package
For detailed information on PCB related thermal and soldering issues of the PG-VQFN-48-15 package see [3],
chapter 3 and 4.
Preliminary Data Sheet 37 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Package Outlines
6.3 PG-DSO-36-15 Package
Figure 25 Package Outline for PG-DSO-36-15 (Plastic Green Dual Small Outline)
Notes
1. Heatslug down version - pin counting counterclockwise (top view)
2. Dimensions in mm
Attention: The heatslug is connected to VBATH via the chip substrate. Due to the high voltage of up to
150 V between VHR and VBATH, touching of the heatsink or any attached conducting part can
be hazardous.
Bottom View
Does not include plastic or metal protrusion of 0.15 max. per side
118
0.25
±0.1
1.1
36
+0.13
0.25
36x
19
M
(Heatslug)
15.74
0.65
±0.1
CAB
19
C
3.25
3.5 MAX.
+0.1
0
0.1
±0.1
36
2.8
B
11
±0.15 1)
1.3
5˚
0.25
±3˚
-0.02
+0.07
6.3
14.2
(Mold)
±0.3
B
±0.15
0.25
Heatslug
0.95
Heatslug
±0.1
5.9
3.2
(Metal)
±0.1
(Metal)
13.7
(Metal)
10 1
-0.2
Index Marking
(Mold)
15.9
1)
±0.1
A
1 x 45˚
1)
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
Package Outlines
Preliminary Data Sheet 38 Revision 2.0, 2006-10-10
6.3.1 Recommended PCB Foot Print Pattern for PG-DSO-36-15 Package
The heatslug is soldered to the PCB according to Figure 25. For improved thermal behaviour the utilization of
another PCB metal layer as an additional cooling area is recommended. These copper areas should be both
electrically separated from each other and floating, i. e. they must not be connected with any other metallic part
on the PCB.
Figure 26 Footprint for PG-DSO-36-15
Flash Au recommended, free of solder resist
Cu layer with solder resist coating
5.9
3.21.83
13.48
0.33
0.65
13.7
15.9
9.5
Via hole
Package outline
Heatslug outline
Preliminary Data Sheet 39 Revision 2.0, 2006-10-10
SLIC-E / TSLIC-E
PEF 4265 / PEF 4365
References
References
[1] SLIC-E/-E2 / TSLIC-E (PEB 4265/-2 / PEB 4365) Application Note “Protection for SLIC-E / -E2 against
Overvoltages and Overcurrents according to ITU-T K. 20/K.21/K.45” Rev. 1.0, 2004-06-29
[2] VINETIC® Version 1.4 Prel. Application Note External Components Rev. 2.0, 2005-09-06
[3] Recommendations for Printed Circuit Board Assembly of Infineon P(G)-VQFN Packages, Application
Support, DS3, 2006-03-03
