CY7C024AV-25AC - Cypress Semiconductor Corp

3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C024AV/025AV/026A

CY7C0241AV/0251AV/036A

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-06052 Rev. *H Revised June 15, 2005

Features

• True dual-ported memory cells which allow

simultaneous access of the same memory location

• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)

• 4/8K × 18 organization (CY7C0241AV/0251AV)

• 16K × 18 organization (CY7C036AV)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 20 an d 25 ns

• Low operatin g pow e r

—Active: ICC = 115 mA (typical)

—Standby: ISB3 = 10 μA (typical)

• Fully asynchronous operation

• Automatic powe r-do wn

• Expandable data bus to 32/36 bits or more using

Master/Slave chip select when using more than one

device

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

•INT

flag for port-to-port communication

• Separate upper-byte and lower-byte control

• Pin select for Master or Slave

• Commercial and industrial temperature ranges

• Available in 100-pin Lead (Pb)-free TQFP and 100-pin

TQFP

Notes:

1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.

2. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.

3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.

4. BUSY is an output in mast er mode and an input in slave mode.

R/WL

OEL

I/O8/9L–I/O15/17L I/O

Control

Address

Decode

A0L–A11/12/13L

CEL

OEL

R/WL

BUSYL

I/O

Control

CEL

Interrupt

Semaphore

Arbitration

SEML

INTL

M/S

UBL

LBL

I/O0L–I/O7/8L

R/WR

OER

I/O8/9L–I/O15/17R

CER

UBR

LBR

I/O0L–I/O7/8R

UBL

LBL

Logic Block Diagram

A0L–A11/1213L True Dual-Ported

RAM Array

A0R–A11/12/13R

CER

OER

R/WR

BUSYR

SEMR

INTR

UBR

LBR

Address

Decode A0R–A11/12/13R

[1] [1]

[2] [2]

[4] [4]

12/13/14

8/9

12/13/14

8/9

12/13/14 12/13/14

[3]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 2 of 19

Pin Configurations

Notes:

5. A12L on the CY7C025AV.

6. A12R on the CY7C025AV.

Top View

100-Pin TQ FP

100 99 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

A5L

A4L

INTL

A2L

A0L

BUSYL

GND

INTR

A0R

A1L

I/O10L

I/O11L

I/O15L

VCC

GND

I/O1R

I/O2R

VCC

9091

A3L

M/S

BUSYR

I/O14L

GND

I/O12L

I/O13L

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

83 82 81 80 79 78 77 76

43 44 45 46 4748 49 50

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

GND

I/O1L

I/O0L

OEL

SEML

VCC

CEL

UBL

LBL

A11L

A10L

A9L

A8L

A7L

A6L

I/O0R

I/O7R

I/O8R

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND

I/O15R

ŒR

R/WR

GND

SEMR

CER

UBR

LBR

A11R

A10R

A9R

A8R

A7R

A6R

A5R

CY7C024AV (4K × 16)

R/WL

[5]

[6]

CY7C025AV (8K × 16)

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 3 of 19

Notes:

7. A12L on the CY7C0251AV.

8. A12R on the CY7C0251AVC.

Pin Configurations (continued)

Top View

100-Pin TQ FP

100 99 9798 96

4241

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

A5L

A4L

INTL

A2L

A0L

BUSYL

GND

INTR

A0R

A1L

I/O11L

I/O12L

I/O16L

VCC

GND

I/O1R

I/O2R

VCC

9091

A3L

M/S

BUSYR

I/O15L

GND

I/O13L

I/O14L

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

83 82 81 80 79 78 77 76

43 44 45 46 47 48 49 50

I/O9L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

I/O10L

GND

I/O1L

I/O0L

OEL

SEML

VCC

CEL

UBL

LBL

A11L

A10L

A9L

A8L

A7L

A6L

I/O0R

I/O7R

I/O16R

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND

I/O15R

R/WR

GND

SEMR

CER

UBR

LBR

A11R

A10R

A9R

A8R

A7R

A6R

A5R

CY7C0241AV (4K × 18)

I/O8L

I/O17L

I/O8R

I/O17R

R/WL

[8] [7]

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A6L

A5L

A4L

INTL

A2L

A0L

GND

M/S

A0R

A1R

A1L

A3L

BUSYR

INTR

A2R

A3R

A4R

A5R

BUSYL

CY7C026AV (16K × 16)

I/O10L

I/O11L

I/O15L

I/O13L

I/O14L

GND

I/O0R

VCC

I/O3R

GND

I/O12L

I/O1R

I/O2R

I/O4R

I/O5R

I/O6R

VCC

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O0L

I/O2L

I/O1L

VCC

R/WL

UBL

LBL

GND

I/O3L

SEML

CEL

A13L

A12L

A11L

A10L

A9L

A8L

A7L

OEL

34 35 36 424139 403837 43 44 45 5048 494746

A6R

A7R

A8R

A9R

A10R

A11R

CER

A13R

UBR

GND

R/WR

GND

I/O14R

LBR

A12R

OER

I/O15R

I/O13R

I/O12R

I/O11R

I/O10R

I/O9R

I/O8R

I/O7R

SEMR

3332313029282726

CY7C0251AV (8K × 18)

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 4 of 19

Pin Configurations (continued)

Top View

100-Pin TQFP

100 99 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

A5L

A4L

INTL

A2L

A0L

BUSYL

GND

INTR

A0R

A1L

I/O11L

I/O12L

I/O16L

VCC

GND

I/O1R

I/O2R

VCC

9091

A3L

M/S

BUSYR

I/O15L

GND

I/O13L

I/O14L

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

83 82 81 80 79 78 77 76

43 44 45 46 4748 49 50

I/O9L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

I/O10L

GND

I/O1L

I/O0L

OEL

SEML

VCC

CEL

UBL

LBL

A11L

A10L

A9L

A8L

A7L

A6L

I/O0R

I/O7R

I/O16R

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND

I/O15R

R/WR

GND

SEMR

CER

UBR

LBR

A11R

A10R

A9R

A8R

A7R

A6R

A5R

I/O8L

I/O17L

I/O8R

I/O17R

R/WL

CY7C036AV (16K × 18)

A13L

A13R

A12L

A12R

Selection Guide

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

-20

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

-25 Unit

Maximum Access T i me 20 25 ns

Typical Operating Current 120 115 mA

Typical S tandby Current for ISB1

(Both ports TTL Level) 35 30 mA

Typical S tandby Current for ISB3

(Both ports CMOS Level) 10 10 μA

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 5 of 19

Architecture

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV consist of an array of 4K, 8K, and 16K words of 16 and

18 bits each of dual-port RAM cells, I/O and address lines, and

control signals (CE, OE, R/W). These control pins permit

independent access for reads or writes to any location in

memory. To handle simultaneous writes/reads to the same

location, a BUSY pin is provided on each port. Two Interru pt

(INT) pins can be utilized for port-to-port communication. T wo

Semaphore (SEM) control pins are used for allocating shared

resources. With the M/S pin, the devices can function as a

master (BUSY pins are outputs) or as a slave (BUSY pins are

inputs). The devices also have an automatic power-down

feature controlled by CE. Each port is provided with its own

output enable control (OE), which allows data to be read from

the device.

Functional Description

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV

/036AV are low-power CMOS 4K, 8K, and 16K ×16/18

dual-port static RAMs. Various arbitration schemes are

included on the devices to handle situations when multiple

processors access the same piece of data. Two ports are

provided, permitting independent, asynchronous access for

reads and writes to any location in memory. The devices can

be utilized as standalone 16/18-bit dual-port static RAMs or

multiple devices can be combined in order to function as a

32/36-bit or wider master/slave dual -port static RAM. An M/S

pin is provided for implementing 32/36-bit or wider memory

applications without the need for separate master and slave

devices or additio nal discre te logic. Ap plication areas include

interprocessor/multiprocessor designs, communications

status buffering, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE),

Read or Write Enable (R/W), and Output Enable (OE). Two

flags are provided on each port (BUSY and INT). BUSY

signals that the port is trying to access the same location

currently being accessed by the other port. Th e Interrupt flag

(INT) permits communication between ports or systems by

means of a mail box. The semaphores are used to pass a flag,

or token, from one port to the other to indicate that a shared

resource is in use. The semaphore logic is comprised of eight

shared latches. Only one side can control the latch

(semaphore) at any time. Control of a semaphore indicates

that a shared resource is in use. An automatic power-down

feature is controlled independently on each port by a Chip

Select (CE) pin.

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV are available in 100-pin Lead (Pb)-free Thin Quad Flat

Pack (TQFP) and 100-pin TQFP.

Write Operation

Data must be set up for a duration of tSD before the rising edge

of R/ W in order to guarantee a valid write. A write operation is

controlled by either the R/W pin (see Write Cycle No. 1

waveform) or the CE pin (see Write Cycle No. 2 waveform).

Required inputs for non-contention operations are summa-

rized in Table 1.

If a location is being written to by one port and the opposite

port attempts to read that location, a port-to-port flowthro ugh

delay must occur before the data is read on the output;

otherwise the data read is not deterministic. Data will be valid

on the port tDDD after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE

and CE pins. Data will be available tACE after CE or tDOE after

OE is asserted. If the user wishes to access a semaphore flag,

then the SEM pin must be asserted instead of the CE pin, and

OE must also be asserted.

Interrupts

The upper two memory locations may be used for message

passing. The highest memory location (FFF for the

CY7C024AV/41AV, 1FFF for the CY7C025AV/51AV, 3FFF for

Pin Definitions

Lef t Port Right Port Description

CELCERChip Enable.

R/WLR/WRRead/Write Enable.

OELOEROutput Enable.

A0L–A13L A0R–A13R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K).

I/O0L–I/O17L I/O0R–I/O17R Dat a Bus Input/Output.

SEML SEMRSemaphore Enable.

UBLUBRUpper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices).

LBLLBRLower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices).

INTLINTRInterrupt Flag.

BUSYLBUSYRBusy Flag.

M/S Master or Slave Select.

VCC Power.

GND Ground.

NC No Connect.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 6 of 19

the CY7C026A V/36A V) is the mailbox for the right port and the

second-highest memory location (FFE for the CY7C024AV/

41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the

CY7C026AV/36AV) is th e mailbox for the left port. When one

port writes to the other port’s mailbox, an interrupt is generated

to the owner. The interrupt is reset when the owner reads the

contents of the mailbox. The message is user defined.

Each port can read the other po rt’s mailbox without resetting

the interrupt. The active state of the busy signal (to a port)

prevents the port from setting the interrupt to the winning port.

Also, an active busy to a port prevents that port from reading

its own mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not

connect the interrupt pin to the processor ’s interrupt request

input pin.

The operati on of the interrupts and their interaction with Busy

are summa rized in Table 2.

Busy

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV provide on-chip arbitration to resolve simultaneous

memory location access (contention). If both ports’ CEs are

asserted and an address match occurs within tPS of each

other, the busy logic will dete rmine which port has access. If

tPS is violated, one port will definitely gain permission to the

location, but it is not predictable which port will get that

permission. BUSY will be asserted tBLA after an address

match or tBLC after CE is taken LOW.

Master/Slave

A M/S pin is provided in order to expand the word width by

configuring the device as either a master or a slave. The BUSY

output of the master is connected to the BUSY input of the

slave. This will allow the device to interface to a master device

with no external components. Writing to slave devices must be

delayed until after the BUSY input has settled (tBLC or tBLA),

otherwise, the slave chip may begin a write cycle during a

contention situation. When tied HIGH, th e M/S pin allows the

device to be used as a master and, therefore, the BUSY line

is an output. BUSY can then be used to send the arbitration

outcome to a slave.

Semaphore Operation

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV provide eight semaphore latch es, which are separate

from the dual-port memory locations. Semaphores are used to

reserve resources that are shared between the two ports. The

state of the semaphore indicates that a resource is in use. For

example, if the left port wants to request a given resource, it

sets a latch by writing a zero to a semaphore location. The left

port then verifies its success in setting the latch by reading it.

After writing to the semaphore, SEM or OE must be

deasserted for tSOP before attempting to read the semaphore.

The semaphore value will be avai lable tSWRD + tDOE after the

rising edge of the semaphore write. If the left port was

successful (reads a zero), it assumes control of the shared

resource, otherwise (reads a one) it assumes the right port has

control and continues to poll the semaphore. When the right

side has relinquished control of the semaphore (by writing a

one), the left side will succeed in gaining control of the

semaphore. If the left side no longer requires the semaphore,

a one is written to cancel its request.

Semaphores are accessed by asserting SEM LOW. The SEM

pin functions as a chip select for the semaphore latches (CE

must remain HIGH during SEM LOW). A0–2 represents the

semaphore address. OE and R/W are used in the same

manner as a normal memory access. When writing or reading

a semaphore, the other add ress pins have no effect.

When writing to the semaphore, o nly I/O0 is used. If a zero i s

written to the left port of an available semaphore, a one will

appear at the same semaphore address on the right port. That

semaphore can now only be modified by the side showing zero

(the left port in this case). If the left port now relinquishes

control by writing a one to the semaphore, the semaphore will

be set to one for both sides. However, if the right port had

requested the semaphore (written a zero) while the left port

had control, the right port would immediately own the

semaphore as soon as the left port released it. Table 3 shows

sample semaphore operations.

When reading a semaphore, all sixteen/eighteen data lines

output the sema phore value. The read value is latched in an

output register to prevent the semaphore from changing state

during a write from the other port. If both ports attempt to

access the semaphore within tSPS of each other, the

semaphore will definitely be obtained by one side or the other,

but there is no guarantee which side will control the

semaphore.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 7 of 19

Table 1. Non-Contending Read/Write

Inputs Outputs

OperationCE R/W OE UB LB SEM I/O9–I/O17 I/O0–I/O8

H X X X X H High Z High Z Deselected: Power-Down

X X X H H H High Z High Z Deselected: Power-Down

L L X L H H Data In High Z Write to Upper Byte Only

L L X H L H High Z Data In Write to Lower Byte Only

L L X L L H Data In Data In Write to Both Bytes

L H L L H H Data Out High Z Read Upper Byte Only

L H L H L H High Z Data Out Read Lower Byte Only

L H L L L H Data Out Data Out Read Both Bytes

X X H X X X High Z High Z Outputs Disabled

H H L X X L Data Out Data Out Read Data in Semaphore Flag

X H L H H L Data Out Data Out Read Data in Semaphore Flag

H X X X L Data In Data In Write DIN0 into Semaphore Flag

X X H H L Data In Data In Write DIN0 into Semaphore Flag

L X X L X L Not Allowed

L X X X L L Not Allowed

Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[9]

Left Port Right Port

Function R/WLCELOELA0L–13LINTLR/WRCEROERA0R–13R INTR

Set Right INTR Flag L L X FFF[12] XXXX X L

[11]

Reset Right INTR Flag X X X X X X L L FFF (or 1/3FFF) H[10]

Set Left INTL Flag XXX X L

[10] L L X 1FFE (or 1/3FFE) X

Reset Left INTL Flag X L L 1FFE[12] H

[11] XXX X X

Table 3. Semaphore Operation Example

Function I/O0–I/O17 Left I/O0–I/O17 Right Status

No action 1 1 Semaphore-free

Left port writes 0 to semaphore 0 1 Left Port has semaphore token

Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore

Left port writes 1 to semaphore 1 0 Right port obtains semaphore token

Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore

Right port writes 1 to semaphore 0 1 Left port obtains semaphore token

Left port writes 1 to semaphore 1 1 Semaphore-free

Right port writes 0 to semaphore 1 0 Right port has semaphore token

Right port writes 1 to semaphore 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left port has semaphore token

Left port writes 1 to semaphore 1 1 Semaphore-free

Notes:

9. See Functional Descri ption for specific highest memory locations by device.

10. If BUSYR=L, then no ch ange.

11. If BUSYL=L, then no change.

12. See Functional Descri ption for specific addresses by device.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 8 of 19

Maximum Ratings[13]

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5 V to +4.6V

DC Voltage Applied to

Outputs in High-Z State..........................–0.5V to VCC + 0.5V

DC Input Voltage[14]...............................–0.5V to VCC + 0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 2001V

Latch-up Current............... ... ... ............................... > 200 mA

Operating Range

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V ± 300 mV

Industrial[15] –40°C to +85°C 3.3V ± 300 mV

Electrical Characteristics Over the Operating Range

Parameter Description

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Unit

-20 -25

Min. Typ. Max. Min. Typ. Max.

VOH Output HIGH Voltage (VCC=3.3V) 2.4 2.4 V

VOL Output LOW Voltage 0.4 0.4 V

VIH Input HIGH Voltage 2.0 2.0 V

VIL Input LOW Voltage –0.3[16] 0.8 0.8 V

IOZ Output Leakage Current –10 10 –10 10 μA

IIX Input Leakage Current –10 10 –10 10 μA

ICC Operating Current (VCC = Max.,

IOUT = 0 mA) Outputs Disabled Com’l. 120 175 115 165 mA

Ind.[15] 135 185 mA

ISB1 Standby Current (Both Ports TTL Level)

CEL & CER ≥ VIH, f = fMAX Com’l. 35 45 30 40 mA

Ind.[15] 40 50 mA

ISB2 Standby Current (One Port TTL Level)

CEL | CER ≥ VIH, f = fMAX Com’l. 75 110 65 95 mA

Ind.[15] 75 105 mA

ISB3 Standby Current (Both Ports CMOS Level)

CEL & CER ≥ VCC−0.2V, f = 0 Com’l. 10 500 10 500 μA

Ind.[15] 10 500 μA

ISB4 Standby Current (One Port CMOS Level)

CEL | CER ≥ VIH, f = fMAX[17] Com’l. 70 95 60 80 mA

Ind.[15] 70 90 mA

Capacitance[18]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 2 5°C, f = 1 MHz,

VCC = 3.3V 10 pF

COUT Output Capacitance 10 pF

Notes:

13. The Voltage on any input or I/O pin can not exceed the power pin during power-up.

14. Pul se width < 20 ns.

15. Industrial parts are available in CY7C026AV and CY7C036AV only.

16. VIL > –1.5V for pulse width less than 10ns.

17. fMAX = 1/tRC = All input s cycling at f = 1 /tRC (except output enable) . f = 0 means no add ress or cont rol line s change. This a pplies o nly to inp ut s at CMOS level

standby ISB3.

18. Tested initially and after any design or process changes that may affect these parameters.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 9 of 19

AC Test Loads and Waveforms

3.0V

GND 90% 90%

10%

3ns 3ns

10%

ALL INPUTPULSES

(a) Normal Load (Load 1)

R1 = 590Ω

OUTPUT

R2 = 435Ω

C= 30pF

VTH =1.4V

OUTPUT

C= 30pF

(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)

R1 = 590Ω

R2 = 435Ω

3.3V

OUTPUT

C= 5pF

RTH = 250Ω

≤≤

including scope and jig)

(Used for tLZ, tHZ, tHZWE, and tLZWE

Switching Characteristics Over the Operating Range [19]

Parameter Description

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Unit

-20 -25

Min. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 20 25 ns

tAA Address to Data Valid 20 25 ns

tOHA Output Hold From Address Change 3 3 ns

tACE[20] CE LOW to Data Valid 20 25 ns

tDOE OE LOW to Data Valid 12 13 ns

tLZOE[21, 22, 23] OE Low to Low Z 3 3 ns

tHZOE[21, 22, 23] OE HIGH to High Z 12 15 ns

tLZCE[21, 22, 23] CE LOW to Low Z 3 3 ns

tHZCE[21, 22, 23] CE HIGH to High Z 12 15 ns

tPU[23] CE LOW to Power-Up 0 0 ns

tPD[23] CE HIGH to Power-Down 20 25 ns

tABE[20] Byte Enable Access T ime 20 25 ns

Write Cycle

tWC Write Cycle Time 20 25 ns

tSCE[20] CE LOW to Write End 15 20 ns

tAW Address Valid to Write End 15 20 ns

tHA Address Hold From Write End 0 0 ns

tSA[20] Address Set-up to Write Start 0 0 ns

tPWE Write Pulse Width 15 20 ns

Notes:

19. Test conditions assume signal transition time of 3 ns or l ess, timing ref erence levels of 1. 5V, input pulse levels of 0 to 3. 0V, and output loading of the specifie d

IOI/IOH and 30-pF load capacitance.

20. To access RAM, CE = L, UB = L, SEM = H . T o access semaphore, C E = H and SEM = L. Either condition must be valid for the entire tSCE time.

21. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

22. Test conditions used are Load 3.

23. This parameter is guarant eed but not tested. For information on port-to-port delay through RAM cells from wri ting port to reading port, refer to Read Timing

with Busy waveform.

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 10 of 19

Data Retention Mode

The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/

036AV are designed with battery backup in mind. Data

retention voltage and supply current are guaranteed over

temperature. The following rules ensure data retention:

1. Chip Enable (C E) must be held HIGH during data retention,

within VCC to VCC – 0.2V.

2. CE must be kept between VCC – 0.2V and 70% of VCC

during the power-up and power-down transitions .

3. The RAM can beg in operation >tRC after V CC reaches the

minimum operating voltage (3.0V).

Notes:

24. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.

25. Test conditions used are Load 2.

26. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).

27. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guarant eed but not tested.

tSD Data Set-up to Write End 15 15 ns

tHD Data Hold From Write End 0 0 ns

tHZWE[22, 23] R/W LOW to High Z 12 15 ns

tLZWE[22, 23] R/W HIGH to Low Z 3 0 ns

tWDD[24] Write Pulse to Data Delay 45 50 ns

tDDD[24] Write Data Valid to Read Data Valid 30 35 ns

Busy Timing[25]

tBLA BUSY LOW from Address Match 20 20 ns

tBHA BUSY HIGH from Address Mismatch 20 20 ns

tBLC BUSY LOW from CE LOW 20 20 ns

tBHC BUSY HIGH from CE HIGH 17 17 ns

tPS Port Set-up for Priority 5 5 ns

tWB R/W HIGH after BUSY (Slave) 0 0 ns

tWH R/W HIGH after BUSY HIGH (Slave) 15 17 ns

tBDD[26] BUSY HIGH to Data Valid 20 25 ns

Interrupt Timing[25]

tINS INT Set Time 20 20 ns

tINR INT Reset Time 20 20 ns

Semaphore Timing

tSOP SEM Flag Update Pulse (OE or SEM)10 12 ns

tSWRD SEM Flag Write to Read Time 5 5 ns

tSPS SEM Flag Contention Window 5 5 ns

tSAA SEM Address Access Time 20 25 ns

Switching Characteristics Over the Operating Range (continued)[19]

Parameter Description

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Unit

-20 -25

Min. Max. Min. Max.

Timing

Parameter Test Conditions[27] Max. Unit

ICCDR1 @ VCCDR = 2V 50 μA

Data Retention Mode

3.0V 3.0V

VCC > 2.0V

VCC to VCC –0.2V

VCC

tRC

VIH

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 11 of 19

Switching Waveforms

Notes:

28. R/W is HIGH for read cycles.

29. Device is continuously selected CE = VIL and UB or LB = VIL. This wavef orm cannot be used f or semaphore rea ds.

30. OE = VIL.

31. Address valid prior to or coincident with CE transition LOW.

32. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

tRC

tAA

tOHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

tOHA

Read Cycle No. 1 (Either Port Address Access)[28, 29, 30]

tACE

tLZOE

tDOE

tHZOE

tHZCE

DATA VALID

tLZCE

tPU tPD

ISB

ICC

DATA OUT

CE and

LB or UB

CURRENT

Read Cycle No. 2 (Either Port CE/OE Access)[28, 31, 32]

UB or LB

DATAOUT

tRC

ADDRESS

tAA tOHA

tLZCEtABE

tHZCE

tACE

tLZCE

Read Cycle No. 3 (Either Port) [28, 30, 31, 32]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 12 of 19

Notes:

33. R/W must be HIGH during all address transiti ons.

34. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.

35. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

36. If OE is LOW during a R/W controlled write cycle, the write pulse wid th must be the larger of tPWE or (tHZWE + tSD) to allow t he I/O drivers to tur n off and da ta

to be placed on t he bus for the r equired tSD. If OE is HIGH duri ng an R/W cont rolled write cycle, this requireme nt does not apply and the wr ite pul se can be

as short as the specified tPWE.

37. To access RAM, CE = VIL, SEM = VIH.

38. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.

To access lower byte, CE = VIL, LB = VIL, SEM = VIH.

39. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.

40. During this period, the I/O pins are in the output state, and input signals must not be applied.

41. If the CE or SEM LOW transition occurs simulta neously with or after the R/W LOW transition, the outputs remain in the high-impedance stat e.

Switching Waveforms (continued)

tAW

tWC

tPWE

tHD

tSD

tHA

R/W

DATAOUT

DATA IN

ADDRESS

tHZOE

tSA

tHZWE tLZWE

Write Cycle No. 1: R/W Controlled Timing[33, 34, 35, 36]

[39]

[36]

[37, 38]

NOTE 40 NOTE 40

tAW

tWC

tSCE

tHD

tSD

tHA

R/W

DATA IN

ADDRESS

tSA

Write Cycle No. 2: CE Controll ed Timing[33, 34, 35, 41]

[37, 38]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 13 of 19

Notes:

42. CE = HIGH for the duration of the above timing (both write and read cycle).

43. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

44. Semaphores are reset (available to both ports) at cycle start.

45. If tSPS is violated, the semaphore will definitely be obtained by one si de or the other, but which side will get the semaphore is unpredictable.

Switching Waveforms (continued)

tSOP

tSAA

VALID ADRESS VALID ADRESS

tHD

DATAIN VALID DATAOUT VALID

tOHA

tAW tHA tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITE CYCLE READ CYCLE

R/W

I/O0

SEM

A0–A2

Semaphore Read After Write Timing, Either Side[42]

MATCH

tSPS

A0L–A2L

MATCH

R/WL

SEML

A0R–A2R

R/WR

SEMR

Timing Diagram of Semaphore Contention[43, 44, 45]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 14 of 19

Note:

46. CEL = CER = LOW.

Switching Waveforms (continued)

VALID

tDDD

tWDD

MATCH

R/WR

DATA INR

DATAOUTL

tWC

ADDRESSR

tPWE

VALID

tSD tHD

ADDRESSL

tPS

tBLA tBHA

tBDD

BUSYL

Timing Diagram of Read with BUSY (M/S=HIGH)[46]

tPWE

R/W

BUSY tWB tWH

Wri te Timing with Busy Input (M/S=LOW)

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 15 of 19

Note:

47. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

Switching Waveforms (continued)

ADDRESS MATCH

tPS

tBLC tBHC

ADDRESS MATCH

tPS

tBLC tBHC

CERValidFirst:

ADDRESSL,R

BUSYR

CEL

CER

BUSYL

CER

CEL

ADDRESSL,R

Busy Timing Diagram No.1 (CE Arbitration)[47]

CELValid First:

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDRESS MISMATCH

tRC or tWC

tBLA tBHA

ADDRESSR

ADDRESS MATCH ADDRESS MISMATCH

tPS

ADDRESSL

BUSYL

tRC or tWC

tBLA tBHA

ADDRESSR

Right AddressValid First:

Busy Timing Diagram No.2 (Address Arbitration)

[47]

Left Address Valid First:

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 16 of 19

Notes:

48. tHA depends on which enable pin (CE L or R/WL) is deasserted first.

49. tINS or tINR depends on which enable pin (CEL or R/WL) is asser ted last.

Switching Waveforms (continued)

Interrupt Timing Diagrams

WRITE 1FFF (OR 1/3FFF)

tWC

Right SideClears INTR:

tHA

READ 7FFF

tRC

tINR

WRITE 1FFE (OR 1/3FFE)

tWC

Right SideSets INTL:

Left Side Sets INTR:

Left SideClears INTL:

READ 7FFE

tINR

tRC

ADDRESSR

CE L

R/WL

INTL

OEL

ADDRESSR

R/WR

CER

INTL

ADDRESSR

CER

R/WR

INTR

OER

ADDRESSL

R/WL

CEL

INTR

tINS

tHA

tINS

(OR 1/3FFF)

OR 1/3FFE)

[48]

[49]

[48]

[49]

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 17 of 19

Ordering Information

4K x16 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

15 CY7C024AV-15AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C024AV-15AXI A100 100-Pin Lead-free Thin Quad Flat Pack

20 CY7C024AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C024AV-20AXC A100 100-Pin Lead-free Thin Quad Flat Pack

CY7C024AV-20AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C024AV-20AXI A100 100-Pin Lead-free Thin Quad Flat Pack

25 CY7C024AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C024AV-25AXC A100 100-Pin Lead-free Thin Quad Flat Pack

CY7C024AV-25AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C024AV-25AXI A100 100-Pin Lead-free Thin Quad Flat Pack

8K x16 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C025AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C025AV-20AXC A100 100-Pin Lead-free Thin Quad Flat Pack

CY7C025AV-20AXI A100 100-Pin Lead-free Thin Quad Flat Pack Industrial

25 CY7C025AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C025AV-25AXC A100 100-Pin Lead-free Thin Quad Flat Pack

CY7C025AV-25AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C025AV-25AXI A100 100-Pin Lead-free Thin Quad Flat Pack

16K x16 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C026AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C026AV-20AXC A100 100-Pin Lead-free Thin Quad Flat Pack

CY7C026AV-20AXI A100 100-Pin Lead-free Thin Quad Flat Pack Industrial

25 CY7C026AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C026AV-25AXC A100 100-Pin Lead-free Thin Quad Flat Pack

CY7C026AV-25AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C026AV-25AXI A100 100-Pin Lead-free Thin Quad Flat Pack

4K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C0241AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C0241AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

8K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C0251AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C0251AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 18 of 19

© Cypress Semi con duct or Cor po rati on , 20 05 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All product and company names mentioned in this document are the trademarks of their respective holders.

16K x18 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

20 CY7C036AV-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C036AV-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C036AV-25AXC A100 100-Pin Lead-free Thin Quad Flat Pack

CY7C036AV-25AI A100 100-Pin Thin Quad Flat Pack Industrial

Package Diagram

100-Pin Thin Plastic Quad Flat Pack (TQFP) A10 0

51-85048-*B

100-Pin Lead (Pb)-free Thin Plastic Quad Flat Pack (TQFP) A100

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *H Page 19 of 19

Document History Page

Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036A V 3.3V 4K/8K/16K x 16/18

Dual Port Static RAM

Document Number: 38-06052

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 110204 11/11/01 SZV Change from Spec number: 38-00838 to 38-06052

*A 122302 12/27/02 RBI Power-up requirements added to Maximum Ratings Information

*B 128958 9/03/03 JFU Added CY7C025AV-25AI to Ordering Information

*C 237622 See ECN YDT Removed cross information from features section

*D 241968 See ECN WWZ Added CY7C024AV-25AI to Ordering Information

*E 276451 See ECN SPN Corrected x18 for 026AV to x16

*F 279452 See ECN RUY Added lead (Pb)-free packaging information

Corrected pin A113L to A13L on CY7C026AV pin list

Added minimum VIL of 0.3V and note 16

*G 373580 See ECN RUY Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Infor-

mation

*H 380476 See ECN PCX Added to Part Ordering info rmation:

CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI,

CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI