CY2305/CY2309 Low Cost 3.3 V Zero Delay Buffer Low Cost 3.3 V Zero Delay Buffer Features Functional Description 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies Zero input-output propagation delay 60-ps typical cycle-to-cycle jitter (high drive) Multiple low skew outputs 85 ps typical output-to-output skew One input drives five outputs (CY2305) One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309) Compatible with Pentium-based systems Test Mode to bypass phase-locked loop (PLL) (CY2309) Packages: 8-pin, 150-mil SOIC package (CY2305) 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309) 3.3 V operation Commercial and industrial temperature ranges The CY2309 is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in "Select Input Decoding" on page 5. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY2305 and CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0 A current draw for these parts. The CY2309 PLL shuts down in one additional case as shown in "Select Input Decoding" on page 5. Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY2305/CY2309 is available in two or three different configurations, as shown in "Ordering Information" on page 16. The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. For a complete list of related documentation, click here. Logic Block Diagram PLL MUX REF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 S2 Select Input Decoding CLKB2 CLKB3 S1 CLKB4 Cypress Semiconductor Corporation Document Number: 38-07140 Rev. *U * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 5, 2016 CY2305/CY2309 Contents Pin Diagram ....................................................................... 3 Pin Description ................................................................. 3 Pin Diagram ....................................................................... 4 Pin Description ................................................................. 4 Select Input Decoding ...................................................... 5 Zero Delay and Skew Control .......................................... 5 Absolute Maximum Conditions ....................................... 6 Operating Conditions ....................................................... 6 Electrical Characteristics ................................................. 6 Switching Characteristics ................................................ 7 Switching Characteristics ................................................ 8 Operating Conditions ....................................................... 9 Electrical Characteristics ................................................. 9 Switching Characteristics .............................................. 10 Switching Characteristics .............................................. 11 Switching Waveforms .................................................... 12 Typical Duty Cycle and IDD Trends ............................... 13 Typical Duty Cycle and IDD Trends .............................. 14 Test Circuits .................................................................... 15 Document Number: 38-07140 Rev. *U Ordering Information ...................................................... 16 Ordering Information ...................................................... 16 Ordering Code Definitions ......................................... 17 Package Drawing and Dimensions ............................... 18 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Errata ............................................................................... 21 Part Numbers Affected .............................................. 21 CY2305/CY2309 Errata Summary ............................ 22 CY2305/CY2309 Qualification Status ....................... 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 25 Worldwide Sales and Design Support ....................... 25 Products .................................................................... 25 PSoC(R) Solutions ...................................................... 25 Cypress Developer Community ................................. 25 Technical Support ..................................................... 25 Page 2 of 25 CY2305/CY2309 Pin Diagram Figure 1. Pin Diagram - CY2305 REF CLK2 CLK1 GND 1 8 2 7 3 6 4 5 CLKOUT CLK4 VDD CLK3 Pin Description For CY2305 Pin Signal Description Input reference frequency, 5-V tolerant input 1 REF 2 CLK2[2] Buffered clock output 3 CLK1[2] Buffered clock output 4 GND Ground 5 CLK3[2] Buffered clock output 6 VDD 3.3-V supply 7 CLK4[2] Buffered clock output 8 CLKOUT[2] Buffered clock output, internal feedback on this pin [1] Notes 1. Weak pull down. 2. Weak pull down on all outputs. Document Number: 38-07140 Rev. *U Page 3 of 25 CY2305/CY2309 Pin Diagram Figure 2. Pin Diagram - CY2309 REF CLKA1 1 16 2 15 CLKA2 VDD 3 14 4 13 GND CLKB1 CLKB2 S2 5 12 6 11 7 10 8 9 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Pin Description For CY2309 Pin Signal Description 1 REF[3] Input reference frequency, 5-V tolerant input 2 CLKA1[4] Buffered clock output, Bank A 3 CLKA2[4] Buffered clock output, Bank A 4 VDD 3.3-V supply 5 GND Ground 6 CLKB1[4] Buffered clock output, Bank B 7 CLKB2[4] Buffered clock output, Bank B 8 S2[5] Select input, bit 2 9 S1[5] Select input, bit 1 10 CLKB3[4] Buffered clock output, Bank B 11 CLKB4[4] Buffered clock output, Bank B 12 GND Ground 13 VDD 3.3-V supply 14 CLKA3[4] Buffered clock output, Bank A 15 CLKA4 [4] Buffered clock output, Bank A 16 CLKOUT[4] Buffered output, internal feedback on this pin Notes 3. Weak pull down. 4. Weak pull down on all outputs. 5. Weak pull ups on these inputs. Document Number: 38-07140 Rev. *U Page 4 of 25 CY2305/CY2309 Select Input Decoding For CY2309 CLKOUT [6] S2 S1 CLOCK A1-A4 CLOCK B1-B4 Output Source PLL Shutdown 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins Zero Delay and Skew Control All outputs must be uniformly loaded to achieve zero delay between the input and output. Because the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay adjustments are required, use Figure 3 to calculate loading differences between the CLKOUT pin and other outputs. Note 6. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document Number: 38-07140 Rev. *U Page 5 of 25 CY2305/CY2309 Absolute Maximum Conditions Storage temperature .................................. -65C to +150C Junction temperature ................................................. 150C Supply voltage to ground potential ..............-0.5 V to +7.0 V Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2,000 V DC input voltage (Except REF) .......... -0.5 V to VDD + 0.5 V DC input voltage REF .......................................-0.5 V to 7 V Operating Conditions For CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter Description Min Max Unit 3.0 3.6 V 0 70 C VDD Supply voltage TA Operating temperature (ambient temperature) CL Load capacitance, below 100 MHz - 30 pF CL Load capacitance, from 100 MHz to 133 MHz - 10 pF CIN Input capacitance tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) - 7 pF 0.05 50 ms Min Max Unit - 0.8 V Electrical Characteristics For CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter VIL Description Input LOW voltage [7] [7] VIH Input HIGH voltage IIL Input LOW current IIH Input HIGH current VOL Output LOW voltage [8] Output HIGH voltage [8] Test Conditions 2.0 - V VIN = 0 V - 50.0 A VIN = VDD - 100.0 A IOL = 8 mA (-1) - 0.4 V 2.4 - V IOH = 12 mA (-1H) VOH IOH = -8 mA (-1) IOL = -12 mA (-1H) IDD (PD mode) Power-down supply current REF = 0 MHz - 12.0 A IDD Unloaded outputs at 66.67 MHz, SEL inputs at VSS - 32.0 mA Supply current Notes 7. REF input has a threshold voltage of VDD/2. 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07140 Rev. *U Page 6 of 25 CY2305/CY2309 Switching Characteristics For CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices Parameter [9] t1 Description Test Conditions Output frequency 30-pF load 10-pF load [10] tDC Duty cycle t3 Rise time [10] t4 Fall time [10] [10] Typ Max Unit 10 - 100 MHz 10 - 133.33 MHz 40.0 50.0 60.0 % Measured between 0.8 V and 2.0 V - - 2.50 ns Measured between 0.8 V and 2.0 V - - 2.50 ns All outputs equally loaded - 85 250 ps Measured at 1.4 V, Fout = 66.67 MHz = t2 t1 Min t5 Output-to-output skew t6A Delay, REF rising edge to CLKOUT rising edge [10] Measured at VDD/2 - 0 350 ps t6B Delay, REF rising edge to CLKOUT rising edge [10] Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. 1 5 8.7 ns t7 Device-to-device skew [10] Measured at VDD/2 on the CLKOUT pins of devices - - 700 ps tJ Cycle-to-cycle jitter [10] Measured at 66.67 MHz, loaded outputs - 70 200 ps tLOCK PLL lock time [10, 11, 12] Stable power supply, valid clock presented on REF pin - - 1.0 ms Notes 9. All parameters specified with loaded outputs. 10. Parameter is guaranteed by design and characterization. Not 100% tested in production. 11. The clock outputs are undefined until PLL is locked. 12. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 s, Figure 9. Document Number: 38-07140 Rev. *U Page 7 of 25 CY2305/CY2309 Switching Characteristics For CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices Parameter [13] t1 Description Output frequency Condition 30 pF load 10 pF load Min Typ Max Unit 10 - 100 MHz 10 - 133.33 MHz Measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0 % Duty cycle [14] = t2 t1 Measured at 1.4 V, Fout < 50 MHz 45.0 50.0 55.0 % t3 Rise time [14] Measured between 0.8 V and 2.0 V - - 1.50 ns t4 Fall time [14] Measured between 0.8 V and 2.0 V - - 1.50 ns t5 Output-to-output skew [14] All outputs equally loaded - 85 250 ps t6A Delay, REF rising edge to CLKOUT rising edge [14] Measured at VDD/2 - - 350 ps t6B Delay, REF rising edge to CLKOUT rising edge [14] Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. 1 5 8.7 ns t7 Device-to-device skew [14] Measured at VDD/2 on the CLKOUT pins of devices - - 700 ps t8 Output slew rate [14] Measured between 0.8 V and 2.0 V using Test Circuit #2 1 - tJ Cycle-to-cycle jitter [14] Measured at 66.67 MHz, loaded outputs - 60 200 ps tLOCK PLL lock time [14, 15, 16] Stable power supply, valid clock presented on REF pin - - 1.0 ms tDC Duty cycle tDC [14] = t2 t1 V/ns Notes 13. All parameters specified with loaded outputs. 14. Parameter is guaranteed by design and characterization. Not 100% tested in production. 15. The clock outputs are undefined until PLL is locked. 16. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 s, Figure 9. Document Number: 38-07140 Rev. *U Page 8 of 25 CY2305/CY2309 Operating Conditions For CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices Parameter Description Min Max Unit VDD Supply voltage 3.0 3.6 V TA Operating temperature (ambient temperature) -40 85 C CL Load capacitance, below 100 MHz - 30 pF CL Load capacitance, from 100 MHz to 133 MHz - 10 pF CIN Input capacitance - 7 pF Electrical Characteristics For CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices Parameter Min Max Unit Input LOW voltage [17] - 0.8 V VIH Input HIGH voltage [17] 2.0 - V IIL Input LOW current VIN = 0 V - 50.0 A IIH Input HIGH current VIN = VDD - 100.0 A IOL = 8 mA (-1) - 0.4 V 2.4 - V REF = 0 MHz - 25.0 A Unloaded outputs at 66.67 MHz, SEL inputs at VSS - 35.0 mA VIL VOL Description Output LOW voltage [18] Output HIGH voltage [18] Test Conditions IOH =12 mA (-1H) VOH IOH = -8 mA (-1) IOL = -12 mA (-1H) IDD (PD mode) Power-down supply current IDD Supply current Notes 17. REF input has a threshold voltage of VDD/2. 18. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07140 Rev. *U Page 9 of 25 CY2305/CY2309 Switching Characteristics For CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices Parameter [19] t1 Description Output frequency Test Conditions 30 pF load 10 pF load Min Typ Max Unit 10 - 100 MHz 10 - 133.33 MHz Measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0 % Rise time [20] Measured between 0.8 V and 2.0 V - - 2.50 ns t4 Fall time [20] Measured between 0.8 V and 2.0 V - - 2.50 ns t5 Output-to-output skew [20] All outputs equally loaded - 85 250 ps t6A Delay, REF rising edge to CLKOUT rising edge [20] Measured at VDD/2 - - 350 ps t6B Delay, REF rising edge to CLKOUT rising edge [20] Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. 1 5 8.7 ns t7 Device-to-device skew [20] Measured at VDD/2 on the CLKOUT pins of devices - - 700 ps tJ Cycle-to-cycle jitter [20] Measured at 66.67 MHz, loaded outputs - 70 200 ps tLOCK PLL lock time [20, 21, 22] Stable power supply, valid clock presented on REF pin - - 1.0 ms tDC Duty cycle t3 [20] = t2 t1 Notes 19. All parameters specified with loaded outputs. 20. Parameter is guaranteed by design and characterization. Not 100% tested in production. 21. The clock outputs are undefined until PLL is locked. 22. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 s, Figure 9. Document Number: 38-07140 Rev. *U Page 10 of 25 CY2305/CY2309 Switching Characteristics For CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices Parameter [23] t1 Description Output frequency Conditions 30 pF load 10 pF load Min Typ Max Unit 10 - 100 MHz 10 - 133.33 MHz Measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0 % Duty cycle [24] = t2 t1 Measured at 1.4 V, Fout < 50 MHz 45.0 50.0 55.0 % t3 Rise time [24] Measured between 0.8 V and 2.0 V - - 1.50 ns t4 Fall time [24] Measured between 0.8 V and 2.0 V - - 1.50 ns t5 Output-to output skew [24] All outputs equally loaded - 85 250 ps t6A Delay, REF rising edge to CLKOUT rising edge [24] Measured at VDD/2 - - 350 ps t6B Delay, REF rising edge to CLKOUT rising edge [24] Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. 1 5 8.7 ns t7 Device-to-device skew [24] Measured at VDD/2 on the CLKOUT pins of devices - - 700 ps t8 Output slew rate [24] Measured between 0.8 V and 2.0 V using Test Circuit #2 1 - - V/ns tJ Cycle-to-cycle jitter [24] Measured at 66.67 MHz, loaded outputs - 60 200 ps tLOCK PLL lock time [24, 25, 26] Stable power supply, valid clock presented on REF pin - - 1.0 ms tDC Duty cycle tDC [24] = t2 t1 Notes 23. All parameters specified with loaded outputs. 24. Parameter is guaranteed by design and characterization. Not 100% tested in production. 25. The clock outputs are undefined until PLL is locked. 26. For on the fly change in reference input frequency, PLL lock time is only guaranteed when stop time between change in input reference frequency is > 10 s, Figure 9. Document Number: 38-07140 Rev. *U Page 11 of 25 CY2305/CY2309 Switching Waveforms Figure 4. Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V Figure 5. All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V 2.0 V 0.8 V 3.3 V 0V t4 t3 Figure 6. Output-Output Skew OUTPUT 1.4 V 1.4 V OUTPUT t5 Figure 7. Input-Output Propagation Delay INPUT VDD/2 VDD/2 OUTPUT t6 Figure 8. Device-Device Skew CLKOUT, Device 1 VDD/2 VDD/2 CLKOUT, Device 2 t7 Figure 9. Stop Time between Change in Input Reference Frequency Stop Time Document Number: 38-07140 Rev. *U Page 12 of 25 CY2305/CY2309 Typical Duty Cycle and IDD Trends For CY2305-1 and CY2309-1 [27, 28] Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) 60 60 58 58 56 56 54 52 33 MHz 50 66 MHz 48 100 MHz 46 54 Duty Cycle (% ) Duty Cycle (% ) Duty Cycle Vs VD D (for 30 pF Loads over Frequency - 3.3V, 25C) 33 MHz 52 66 MHz 50 100 MHz 48 133 MHz 46 44 44 42 42 40 40 3 3.1 3.2 3.3 3.4 3.5 3.6 3 3.1 3.2 VDD (V) 60 60 58 58 3.5 3.6 56 54 -40C 52 0C 50 25C 48 70C 46 85C Duty Cycle (%) 56 Duty Cycle (%) 3.4 D uty Cycle Vs Fre que ncy (for 15 pF Loads ov e r T e mpe rature - 3.3V) Duty Cycle Vs Fre que ncy (for 30 pF Loads ov e r T e mpe rature - 3.3V) 54 -40C 52 0C 50 25C 48 70C 46 85C 44 44 42 42 40 40 20 40 60 80 100 120 140 20 40 60 Fre que ncy (M Hz) 80 100 120 140 Fre que ncy (M Hz) IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) 140 140 120 120 100 33 MHz 80 66 MHz 60 100 MHz IDD (mA) 100 IDD (mA) 3.3 VDD (V) 33 MHz 80 66 MHz 60 40 40 20 20 100 MHz 0 0 0 1 2 3 4 5 6 # of Loaded Outputs 7 8 9 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs Notes 27. Duty cycle is taken from typical chip measured at 1.4 V. 28. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = frequency (Hz)). Document Number: 38-07140 Rev. *U Page 13 of 25 CY2305/CY2309 Typical Duty Cycle and IDD Trends For CY2305-1H and CY2309-1H [29, 30] Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) Duty Cycle Vs VD D (for 30 pF Loads over Frequency - 3.3V, 25C) 60 58 58 56 56 Duty Cycle (% ) 54 52 33 MHz 50 66 MHz 48 100 MHz 46 Duty Cycle (% ) 60 54 33 MHz 52 66 MHz 50 100 MHz 48 133 MHz 46 44 44 42 42 40 40 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 3.2 3.3 Duty C ycle Vs Fre que ncy (for 30 pF Loads ov e r T e mpe rature - 3.3V) 3.6 D uty C ycle Vs Fre que ncy 60 60 58 58 56 54 -40C 52 0C 50 25C 48 70C 46 85C Duty Cycle (%) Duty Cycle (%) 3.5 (for 15 pF Loads ov e r T e mpe rature - 3.3V) 56 44 54 -40C 52 0C 50 25C 48 70C 46 85C 44 42 42 40 40 20 40 60 80 100 120 140 20 40 60 Fre que ncy (M Hz) 80 100 120 140 Fre que ncy (M Hz) IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) 160 160 140 140 120 120 100 33 MHz 80 66 MHz 60 100 MHz IDD (mA) IDD (mA) 3.4 VDD (V) VDD (V) 100 80 33 MHz 60 66 MHz 100 MHz 40 40 20 20 0 0 0 1 2 3 4 5 6 # of Loaded Outputs 7 8 9 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs Notes 29. Duty cycle is taken from typical chip measured at 1.4 V. 30. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = frequency (Hz)). Document Number: 38-07140 Rev. *U Page 14 of 25 CY2305/CY2309 Test Circuits Figure 10. Test Circuits Test Circuit # 1 Test Circuit # 2 V DD V DD CLK 0.1 F out 0.1 F OUTPUTS 1 k OUTPUTS 10 pF C LOAD V DD 0.1 F GND 1 k V DD GND 0.1 F GND GND For parameter t8 (output slew rate) on -1H devices Document Number: 38-07140 Rev. *U Page 15 of 25 CY2305/CY2309 Ordering Information For CY2305 Ordering Code Package Type Operating Range CY2305SC-1 8-pin SOIC (150 Mils) Commercial CY2305SC-1T 8-pin SOIC (150 Mils) - Tape and Reel Commercial CY2305SXC-1 8-pin SOIC (150 Mils) Commercial CY2305SXC-1T 8-pin SOIC (150 Mils) - Tape and Reel Commercial CY2305SXI-1 8-pin SOIC (150 Mils) Industrial CY2305SXI-1T 8-pin SOIC (150 Mils) - Tape and Reel Industrial CY2305SXC-1H 8-pin SOIC (150 Mils) Commercial CY2305SXC-1HT 8-pin SOIC (150 Mils) - Tape and Reel Commercial CY2305SXI-1H 8-pin SOIC (150 Mils) Industrial CY2305SXI-1HT 8-pin SOIC (150 Mils) - Tape and Reel Industrial Pb-free Ordering Information For CY2309 Ordering Code Package Type Operating Range Pb-free CY2309SXC-1 16-pin SOIC (150 Mils) Commercial CY2309SXC-1T 16-pin SOIC (150 Mils) - Tape and Reel Commercial CY2309SXI-1 16-pin SOIC (150 Mils) Industrial CY2309SXI-1T 16-pin SOIC (150 Mils) - Tape and Reel Industrial CY2309SXC-1H 16-pin SOIC (150 Mils) Commercial CY2309SXC-1HT 16-pin SOIC (150 Mils) - Tape and Reel Commercial CY2309SXI-1H 16-pin SOIC (150 Mils) Industrial CY2309SXI-1HT 16-pin SOIC (150 Mils) - Tape and Reel Industrial CY2309ZXC-1H 16-pin TSSOP (4.4 mm) Commercial CY2309ZXC-1HT 16-pin TSSOP (4.4 mm) - Tape and Reel Commercial CY2309ZXI-1H 16-pin TSSOP (4.4 mm) Industrial CY2309ZXI-1HT 16-pin TSSOP (4.4 mm) - Tape and Reel Industrial Document Number: 38-07140 Rev. *U Page 16 of 25 CY2305/CY2309 Ordering Code Definitions CY 2305 S (X) C - 1 (H) (T) Tape and reel Output Drive: 1 = standard drive 1H = high drive Temperature Range: C = Commercial I = Industrial Package: S = SOIC, leaded Z = TSSOP, leaded SX = SOIC, Pb-free ZX = TSSOP, Pb-free Base device part number 2305 = 5-output zero delay buffer 2309 = 9-output zero delay buffer Company ID: CY = Cypress Document Number: 38-07140 Rev. *U Page 17 of 25 CY2305/CY2309 Package Drawing and Dimensions Figure 11. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *H Document Number: 38-07140 Rev. *U Page 18 of 25 CY2305/CY2309 Package Drawing and Dimensions (continued) Figure 12. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068 51-85068 *E Figure 13. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091 51-85091 *E Document Number: 38-07140 Rev. *U Page 19 of 25 CY2305/CY2309 Acronyms Acronym Document Conventions Description Units of Measure PCI Personal Computer Interconnect PLL Phase Locked Loop C degree Celsius SDRAM Synchronous Dynamic Random Access Memory A microampere SOIC Small Outline Integrated Circuit mA milliampere TSSOP Thin Small Outline Package ms millisecond ZDB Zero Delay Buffer MHz megahertz ns nanosecond Document Number: 38-07140 Rev. *U Symbol Unit of Measure pF picofarad ps picosecond V volt Page 20 of 25 CY2305/CY2309 Errata This section describes the errata for Cypress Zero Delay Clock Buffers of the family CY2305/CY2309. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Device Characteristics CY2305SC-1 All Variants CY2305SC-1T All Variants CY2305SC-1H All Variants CY2305SC-1HT All Variants CY2305SI-1H All Variants CY2305SI-1HT All Variants CY2305SXC-1 All Variants CY2305SXC-1T All Variants CY2305SXI-1 All Variants CY2305SXI-1H All Variants CY2305SXC-1HT All Variants CY2305SXI-1H All Variants CY2305SXI-1HT All Variants CY2309NZSXC-1H All Variants CY2309NZSXC-1HT All Variants CY2309NZSXI-1H All Variants CY2309NZSXI-1HT All Variants CY2309SC-1HT All Variants CY2309SXC-1H All Variants CY2309SXC-1HT All Variants CY2309SXI-1H All Variants CY2309SXI-1HT All Variants CY2309ZC-1H All Variants CY2309ZC-1HT All Variants CY2309ZXC-1H All Variants CY2309ZXC-1HT All Variants CY2309ZXI-1H All Variants CY2309ZXI-1HT All Variants CY2309SXC-1 All Variants CY2309SXC-1T All Variants CY2309SXI-1 All Variants CY2309SXI-1T All Variants CY2309SC-1 All Variants CY2309SC-1T All Variants CY2309SXC-1 All Variants CY2309SXC-1T All Variants CY2309SXI-1 All Variants CY2309SXI-1T All Variants Document Number: 38-07140 Rev. *U Page 21 of 25 CY2305/CY2309 CY2305/CY2309 Errata Summary Items Part Number Silicon Revision Fix Status Start up lock time issue [CY2305] All B Silicon fixed. New silicon available from WW 25 of 2011 Start up lock time issue [CY2309] All B Silicon fixed. New silicon available from WW 10 of 2013 CY2305/CY2309 Qualification Status Product Status: In production Qualification report last updated on 11/27/2012 (http://www.cypress.com/?rID=72595) 1. Start up lock time issue Problem Definition Output of CY2305/CY2309 fails to locks within 1 ms (as per data sheet spec) Parameters Affected PLL lock time Trigger Condition(S) Start up Scope of Impact It can impact the performance of system and its throughput Workaround Apply reference input (RefClk) before power up (VDD) Input noise propagates to output due to absence of reference input signal during power up. If reference input is present during power up, the noise will not propagate to output and device will start normally without problems. Fix Status This issue is due to design marginality. Two minor design modifications have been made to address this problem. Addition of VCO bias detector block as shown in the following figure which keeps comparator power down till VCO bias is present and thereby eliminating the propagation of noise to feedback. Bias generator enhancement for successful initialization. Document Number: 38-07140 Rev. *U Page 22 of 25 CY2305/CY2309 Document History Page Document Title: CY2305/CY2309, Low Cost 3.3 V Zero Delay Buffer Document Number: 38-07140 Revision ECN Orig. of Change Submission Date Description of Change ** 110249 SZV 10/19/01 Change from Spec number: 38-00530 to 38-07140 *A 111117 CKN 03/01/02 Added t6B row to the Switching Characteristics Table; also added the letter "A" to the t6A row Corrected the table title from CY2305SC-IH and CY2309SC-IH to CY2305SI-IH and CY2309SI-IH *B 117625 HWT 10/21/02 Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the ordering information table. Added the Tape and Reel option to all the existing packages: CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT, CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT, CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT *C 121828 RBI 12/14/02 Power up requirements added to Operating Conditions information *D 131503 RGL 12/12/03 Added Lead-free for all the devices in the ordering information table *E 214083 RGL See ECN Added a Lead-free with the new coding for all SOIC devices in the ordering information table *F 291099 RGL See ECN Added TSSOP Lead-free devices *G 390582 RGL See ECN Added typical values for jitter *H 2542461 AESA 07/23/08 Updated template. Added Note "Not recommended for new designs." Added part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1, CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H, CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in ordering information table. Removed part number CY2305SZC-1, CY2305SZC-1T, CY2305SZI-1, CY2305SZI-1T, CY2305SZC-1H, CY2305SZC-1HT, CY2305SZI-1H, CY2305SZI-1HT, CY2309SZC-1, CY2309SZC-1T, CY2309SZI-1, CY2309SZI-1T, CY2309SZC-1H, CY2309SZC-1HT, CY2309SZI-1H, CY2309SZI-1HT, CY2309ZZC-1H, CY2309ZZC-1HT, CY2309ZI-1H, CY2309ZI-1HT, CY2309ZZI-1H, and CY2309ZZI-1HT in Ordering Information table. Changed Lead-Free to Pb-Free. *I 2565153 AESA 09/18/08 Removed part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1, CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H, CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in ordering information table. Removed note references to note 10 in Pb-Free sections of ordering information table. Changed IDD (PD mode) from 12.0 to 25.0 A for commercial temperature devices Deleted Duty Cycle parameters for Fout <50 MHz commercial and industrial devices. *J 2673353 KVM / PYRS 03/13/09 Reverted IDD (PD mode) and Duty Cycle parameters back to the values in revision *H: Changed IDD (PD mode) from 25 to 12 A for commercial devices. Added Duty Cycle parameters for Fout <50 MHz for commercial and industrial devices. Document Number: 38-07140 Rev. *U Page 23 of 25 CY2305/CY2309 Document History Page (continued) Document Title: CY2305/CY2309, Low Cost 3.3 V Zero Delay Buffer Document Number: 38-07140 Revision ECN Orig. of Change Submission Date *K 2904641 KVM 04/05/10 *L 3047136 KVM 10/04/2010 Added table of contents, ordering code definition, Acronyms and Units tables. Updated 16-pin TSSOP package diagram. *M 3146330 CXQ 01/18/2011 Added "Not recommended for new designs" statement to Features on page 1. Added `not recommended for new designs' footnote to all parts in the ordering information table. *N 3241160 BASH 05/09/2011 Added Footnote 9 on page 6 (CDT 97105). Removed first bullet point "Not recommended for new designs. The CY2305C and CY2309C are form, fit, function compatible devices with improved specifications." from Features section. (CDT 99798). Removed Footnote 20 and all its references from document. (CDT 99798). *O 3400613 BASH 10/10/2011 Added Footnote 12 and its reference to all PLL lock time parameters throughout the document. Added Figure 9 for Stop Time Illustration. *P 3859773 AJU 01/07/2013 Updated Ordering Information (Updated part numbers). Updated Ordering Information (Updated part numbers). Updated Package Drawing and Dimensions: spec 51-85068 - Changed revision from *D to *E. *Q 3997602 AJU 05/11/2013 Updated Package Drawing and Dimensions: spec 51-85066 - Changed revision from *E to *F. Added Errata. *R 4124780 CINM 10/24/2013 Updated to new template. Completing Sunset Review. *S 4307827 CINM 03/13/2014 Updated Errata. *T 4578443 TAVA 11/25/2014 Updated Functional Description: Added "For a complete list of related documentation, click here." at the end. Updated Ordering Information (Updated part numbers). Updated Ordering Information (Updated part numbers). *U 5206812 TAVA 04/05/2016 Updated Zero Delay and Skew Control: Updated description. Updated Package Drawing and Dimensions: spec 51-85066 - Changed revision from *F to *H. Updated to new template. Document Number: 38-07140 Rev. *U Description of Change Removed parts CY2305SI-1, CY2305SI-1T, CY2309SI-1, CY2309SI-1H, CY2309SI-1HT, CY2309SI-1T from Ordering Information. Updated Package Diagram Page 24 of 25 CY2305/CY2309 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products ARM(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface Lighting & Power Control cypress.com/interface cypress.com/powerpsoc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/memory cypress.com/psoc cypress.com/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation 2001-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. 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Document Number: 38-07140 Rev. *U Revised April 5, 2016 Page 25 of 25