20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator ADP7118 Data Sheet TYPICAL APPLICATION CIRCUITS ADP7118 VIN = 6V VIN VOUT = 5V VOUT CIN 2.2F COUT 2.2F SENSE/ADJ ON EN OFF SS GND CSS 1nF 11849-001 Low noise: 11 V rms independent of fixed output voltage PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz, VOUT 5 V, VIN = 7 V Input voltage range: 2.7 V to 20 V Maximum output current: 200 mA Initial accuracy: 0.8% Accuracy over line, load, and temperature 1.1%, TJ = -40C to +85C 1.8%, TJ = -40C to +125C Low dropout voltage: 200 mV (typical) at a 200 mA load, VOUT = 5 V User programmable soft start (LFCSP and SOIC only) Low quiescent current, IGND = 50 A (typical) with no load Low shutdown current: 1.8 A at VIN = 5 V, 3.0 A at VIN = 20 V Stable with a small 2.2 F ceramic output capacitor Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V 16 standard voltages between 1.2 V and 5.0 V are available Adjustable output from 1.2 V to VIN - VDO, output can be adjusted above initial set point Precision enable 2 mm x 2 mm, 6-lead LFCSP, 8-Lead SOIC, 5-Lead TSOT Figure 1. ADP7118 with Fixed Output Voltage, 5 V VIN = 7V ADP7118 VIN SENSE/ADJ COUT 2.2F 10k ON EN OFF VOUT = 6V VOUT 2k CIN 2.2F GND SS CSS 1nF 11849-002 FEATURES Figure 2. ADP7118 with 5 V Output Adjusted to 6 V APPLICATIONS Regulation to noise sensitive applications ADC and DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation Supported by ADIsimPower tool GENERAL DESCRIPTION The ADP7118 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed-signal circuits operating from 20 V down to 1.2 V rails. Using an advanced proprietary architecture, the device provides high power supply rejection, low noise, and achieves excellent line and load transient response with a small 2.2 F ceramic output capacitor. The ADP7118 regulator output noise is 11 V rms independent of the output voltage for the fixed options of 5 V or less. The ADP7118 is available in 16 fixed output voltage options. The following voltages are available from stock: 1.2 V (adjustable), 1.8 V, 2.5 V, 3.3 V, and 5.0 V. Additional voltages available by Rev. A special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V, 3.8 V, 4.2 V, and 4.6 V. Each fixed output voltage can be adjusted above the initial set point with an external feedback divider. This allows the ADP7118 to provide an output voltage from 1.2 V to VIN - VDO with high PSRR and low noise. User programmable soft start with an external capacitor is available in the LFCSP and SOIC packages. The ADP7118 is available in a 6-lead, 2 mm x 2 mm LFCSP making it not only a very compact solution, but it also provides excellent thermal performance for applications requiring up to 200 mA of output current in a small, low profile footprint. The ADP7118 is also available in a 5-lead TSOT and an 8-lead SOIC. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP7118 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Applications Information .............................................................. 14 Typical Application Circuits............................................................ 1 ADIsimPower Design Tool ....................................................... 14 General Description ......................................................................... 1 Capacitor Selection .................................................................... 14 Revision History ............................................................................... 2 Programable Precision Enable .................................................. 15 Specifications..................................................................................... 3 Soft Start ...................................................................................... 15 Input and Output Capacitance, Recommended Specifications... 4 Noise Reduction of the ADP7118 in Adjustable Mode......... 16 Absolute Maximum Ratings ............................................................ 5 Current-Limit and Thermal Overload Protection ................. 16 Thermal Data ................................................................................ 5 Thermal Considerations............................................................ 17 Thermal Resistance ...................................................................... 5 Printed Circuit Board Layout Considerations ............................ 20 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 22 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 23 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 12/14--Rev. 0 to Rev. A Changes to Figure 36 to Figure 41................................................ 12 Changes to Figure 44 ...................................................................... 14 9/14--Revision 0: Initial Version Rev. A | Page 2 of 23 Data Sheet ADP7118 SPECIFICATIONS VIN = VOUT + 1 V or 2.7 V, whichever is greater, VOUT = 5 V, EN = VIN, IOUT = 10 mA, CIN = COUT = 2.2 F, CSS = 0 pF, TA = 25C for typical specifications, TJ = -40C to +125C for minimum/maximum specifications, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND SHUTDOWN CURRENT IGND-SD OUTPUT VOLTAGE ACCURACY Output Voltage Accuracy VOUT LINE REGULATION LOAD REGULATION1 SENSE INPUT BIAS CURRENT DROPOUT VOLTAGE2 VOUT/VIN VOUT/IOUT SENSEI-BIAS VDROPOUT START-UP TIME3 SOFT START SOURCE CURRENT CURRENT-LIMIT THRESHOLD4 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis UNDERVOLTAGE THRESHOLDS Input Voltage Rising Input Voltage Falling Hysteresis PRECISION EN INPUT Logic High Logic Low Logic Hysteresis Leakage Current Delay Time OUTPUT NOISE POWER SUPPLY REJECTION RATIO tSTART-UP SSI-SOURCE ILIMIT TSSD TSSD-HYS Test Conditions/Comments Min 2.7 10 Unit V A A A A A A -0.8 -1.2 +0.8 +1.5 % % -1.8 -0.015 +1.8 +0.015 0.004 1000 60 420 % %/V %/mA nA mV mV s A mA IOUT = 0 A IOUT = 10 mA IOUT = 200 mA EN = GND EN = GND, VIN = 20 V EN = GND IOUT = 10 mA, TJ = 25C 100 A < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V, TJ = -40C to +85C 100 A < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V VIN = (VOUT + 1 V) to 20 V IOUT = 100 A to 200 mA 100 A < IOUT < 200 mA VIN = (VOUT + 1 V) to 20 V IOUT = 10 mA IOUT = 200 mA VOUT = 5 V SS = GND Typ 50 80 180 1.8 3.0 250 TJ rising 0.002 10 30 200 380 1.15 360 Max 20 140 190 320 460 150 15 UVLO RISE UVLO FALL UVLO HYS C C 2.69 V V mV 1.30 1.18 V V mV A s V rms dB dB dB 2.2 230 2.7 V VIN 20 V ENHIGH ENLOW ENHYS IEN-LKG tEN-DLY OUT NOISE PSRR 1.15 1.06 EN = VIN or GND From EN rising from 0 V to VIN to 0.1 x VOUT 10 Hz to 100 kHz, all output voltage options 1 MHz, VIN = 7 V, VOUT = 5 V 100 kHz, VIN = 7 V, VOUT = 5 V 10 kHz, VIN = 7 V, VOUT = 5 V 1.22 1.12 100 0.04 80 11 50 68 88 1 Based on an endpoint calculation using 100 A and 200 mA loads. See Figure 7 for typical load regulation performance for loads less than 1 mA. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output voltages above 2.7 V. 3 Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V. 1 2 Rev. A | Page 3 of 23 ADP7118 Data Sheet INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS Table 2. Parameter INPUT AND OUTPUT CAPACITANCE Minimum Capacitance1 Capacitor Effective Series Resistance (ESR) 1 Symbol Test Conditions/Comments Min CMIN RESR TA = -40C to +125C TA = -40C to +125C 1.5 0.001 Typ Max Unit 0.3 F The minimum input and output capacitance must be greater than 1.5 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, while Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. A | Page 4 of 23 Data Sheet ADP7118 ABSOLUTE MAXIMUM RATINGS JA of the package is based on modeling and calculation using a 4-layer board. The JA is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 inches x 3 inches circuit board. See JESD51-7 and JESD51-9 for detailed information on the board construction. Table 3. Parameter Rating VIN to GND -0.3 V to +24 V VOUT to GND -0.3 V to VIN EN to GND -0.3 V to +24 V SENSE/ADJ to GND -0.3 V to +6 V SS to GND -0.3 V to VIN or +6 V (whichever is less) Storage Temperature Range -65C to +150C Junction Temperature (TJ) 150C Operating Ambient Temperature (TA) Range -40C to +125C Soldering Conditions JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. JB is the junction-to-board thermal characterization parameter with units of C/W. The JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance (JB). Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum TJ is calculated from the board temperature (TB) and PD using the formula THERMAL DATA TJ = TB + (PD x JB) Absolute maximum ratings apply individually only, not in combination. The ADP7118 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature of the device is dependent on the ambient temperature, the power dissipation (PD) of the device, and the junction-to-ambient thermal resistance of the package (JA). Maximum TJ is calculated from the TA and PD using the formula TJ = TA + (PD x JA) (2) See JESD51-8 and JESD51-12 for more detailed information about JB. THERMAL RESISTANCE JA, JC , and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 6-Lead LFCSP 8-Lead SOIC 5-Lead TSOT 1 N/A means not applicable. ESD CAUTION (1) Rev. A | Page 5 of 23 JA 72.1 52.7 170 JC 42.3 41.5 N/A1 JB 47.1 32.7 43 Unit C/W C/W C/W ADP7118 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 SENSE/ADJ 2 VOUT 1 5 SS TOP VIEW (Not to Scale) VOUT 2 SENSE/ADJ 3 EXPOSED PAD 4 EN GND 4 NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD CONNECT TO THE GROUND PLANE ON THE BOARD. Figure 3. 6-Lead LFCSP Pin Configuration VIN 1 5 VOUT 4 SENSE/ADJ TOP VIEW (Not to Scale) 8 VIN 7 VIN 6 SS 5 EN NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD CONNECT TO THE GROUND PLANE ON THE BOARD. 11849-003 GND 3 ADP7118 11849-105 6 VIN ADP7118 Figure 5. 8-Lead SOIC Pin Configuration GND 2 TOP VIEW (Not to Scale) EN 3 11849-104 ADP7118 Figure 4. 5-Lead TSOT Pin Configuration Table 5. Pin Function Descriptions 6-Lead LFCSP 1 Pin No. 8-Lead SOIC 1, 2 5-Lead TSOT 5 Mnemonic VOUT 2 3 4 SENSE/ADJ 3 4 4 5 2 3 GND EN 5 6 SS 6 7, 8 Not applicable 1 VIN EP Description Regulated Output Voltage. Bypass VOUT to GND with a 2.2 F or greater capacitor. Sense Input (SENSE). Connect to load. An external resistor divider may also be used to set the output voltage higher than the fixed output voltage (ADJ). Ground. The enable pin controls the operation of the LDO. Drive EN high to turn on the regulator. Drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Soft Start. An external capacitor connected to this pin determines the soft-start time. Leave this pin open for a typical 320 s start-up time. Do not ground this pin. Regulator Input Supply. Bypass VIN to GND with a 2.2 F or greater capacitor. Exposed Pad. The exposed pad on the bottom of the package enhances thermal performance and is electrically connected to GND inside the package. It is recommended that the exposed pad connect to the ground plane on the board. Rev. A | Page 6 of 23 Data Sheet ADP7118 TYPICAL PERFORMANCE CHARACTERISTICS VIN = VOUT + 1 V or 2.7 V, whichever is greater, VOUT = 5 V, IOUT = 10 mA, CIN = COUT = 2.2 F, TA = 25C, unless otherwise noted. 5.05 5.03 5.02 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 250 GROUND CURRENT (A) 5.04 VOUT (V) 300 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 5.01 5.00 4.99 4.98 4.97 200 150 100 50 4.96 85 125 0 JUNCTION TEMPERATURE (C) -40 5.04 180 5.03 160 GROUND CURRENT (A) 200 5.01 5.00 4.99 4.98 140 120 100 80 60 4.97 40 4.96 20 1000 ILOAD (mA) 0 0.1 11849-005 100 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 250 5.01 5.00 4.99 4.98 4.97 200 150 100 50 4.96 4.95 5 10 15 VIN (V) 20 11849-006 VOUT (V) 5.02 1000 Figure 10. Ground Current vs. Load Current (ILOAD) GROUND CURRENT (A) 5.03 100 300 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 5.04 10 ILOAD (mA) Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD) 5.05 1 Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN) 0 5 10 15 VIN (V) Figure 11. Ground Current vs. Input Voltage (VIN) Rev. A | Page 7 of 23 20 11849-009 VOUT (V) 5.02 10 125 Figure 9. Ground Current vs. Junction Temperature 5.05 1 85 25 JUNCTION TEMPERATURE (C) Figure 6. Output Voltage (VOUT) vs. Junction Temperature 4.95 0.1 -5 11849-007 25 11849-008 -5 -40 11849-004 4.95 ADP7118 SHUTDOWN CURRENT (A) 2.0 1000 VIN = 2.7V VIN = 3V VIN = 5V VIN = 6V VIN = 10V VIN = 20V LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA 900 800 GROUND CURRENT (A) 2.5 Data Sheet 1.5 1.0 700 600 500 400 300 0.5 200 -25 0 25 50 75 100 125 TEMPERATURE (C) Figure 12. Shutdown Current vs. Temperature at Various Input Voltages 5.2 5.4 5.6 Figure 15. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 5 V 250 3.35 200 3.33 150 3.31 100 5.0 VIN (V) VOUT (V) 50 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 3.29 3.27 1 10 100 1000 ILOAD (mA) 3.25 11849-011 0 -40 -5 25 85 11849-014 DROPOUT (mV) 0 4.8 11849-010 0 -50 11849-013 100 125 JUNCTION TEMPERATURE (C) Figure 16. Output Voltage (VOUT) vs. Junction Temperature, VOUT = 3.3 V Figure 13. Dropout Voltage vs. Load Current (ILOAD), VOUT = 5 V 3.35 5.05 5.00 3.33 4.95 VOUT (V) 4.85 4.80 LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA 4.70 4.65 4.60 4.8 5.0 5.2 VIN (V) 5.4 5.6 3.31 3.29 3.27 Figure 14. Output Voltage(VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 5 V Rev. A | Page 8 of 23 3.25 0.1 1 10 100 1000 ILOAD (mA) Figure 17. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V 11849-015 4.75 11849-012 VOUT (V) 4.90 Data Sheet ADP7118 3.35 300 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 250 GROUND CURRENT (A) 3.31 3.29 3.27 150 100 5 10 15 20 VIN (V) 0 11849-016 0 0 200 15 20 Figure 21. Ground Current vs. Input Voltage (VIN), VOUT = 3.3 V 300 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 250 DROPOUT (mV) 250 10 VIN (V) Figure 18. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 3.3 V 300 5 11849-019 50 3.25 GROUND CURRENT (A) 200 150 100 200 150 100 50 50 -40 -5 25 85 0 11849-017 0 125 JUNCTION TEMPERATURE (C) 1 10 100 1000 ILOAD (mA) Figure 19. Ground Current vs. Junction Temperature, VOUT = 3.3 V 11849-020 VOUT (V) 3.33 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA Figure 22. Dropout Voltage vs. Load Current (ILOAD), VOUT = 3.3 V 3.4 200 180 3.3 140 3.2 VOUT (V) 120 100 3.1 80 3.0 40 LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA 2.9 20 0 0.1 1 10 100 1000 ILOAD (mA) 2.8 3.1 3.3 3.5 3.7 3.9 VIN (V) Figure 23. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 3.3 V Figure 20. Ground Current vs. Load Current (ILOAD), VOUT = 3.3 V Rev. A | Page 9 of 23 11849-021 60 11849-018 GROUND CURRENT (A) 160 ADP7118 Data Sheet 700 0 LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA -20 -30 400 300 -40 -50 -60 -70 200 -80 100 -90 3.3 3.5 3.7 3.9 VIN (V) -100 0.2 11849-022 0 3.1 Figure 24. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 3.3 V 3.0 -5 25 85 -120 11849-023 -40 125 TEMPERATURE (C) Figure 25. Soft Start (SS) Current vs. Temperature, Multiple Input Voltages, VOUT = 5 V 3.0V 2.0V 1.6V 1.4V 1.2V 1.0V 800mV 700mV 600mV 500mV 10 100 1k 10k 100k 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz -10 -20 PSRR (dB) -30 -50 -60 10M Figure 28. Power Supply Rejection Ratio(PSRR) vs. Frequency, VOUT = 3.3 V, for Various Headroom Voltages 0 3.0V 2.0V 1.6V 1.4V 1.2V 1.0V 800mV 700mV 600mV 1M FREQUENCY (Hz) 11849-026 PSRR (dB) -40 -50 -60 -70 -70 -80 -80 -90 -90 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 10M -100 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 11849-024 -100 Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 1.8 V, for Various Headroom Voltages HEADROOM VOLTAGE (V) 11849-027 SS CURRENT (A) -100 0 PSRR (dB) 2.6 -60 50 -40 2.2 -40 -80 -30 1.8 -20 100 -20 1.4 0 VIN = 2.7V VIN = 5.0V VIN = 10V VIN = 20V 150 -10 1.0 Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, VOUT = 1.8 V,for Different Frequencies 200 0 0.6 HEADROOM VOLTAGE (V) 300 250 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 11849-025 500 -10 PSRR (dB) GROUND CURRENT (A) 600 Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, VOUT = 3.3 V, for Different Frequencies Rev. A | Page 10 of 23 Data Sheet ADP7118 0 -20 -60 3.0V 2.0V 1.6V 1.4V 1.2V 1.0V 800mV 700mV 600mV 500mV -80 -100 -120 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 5 V, for Various Headroom Voltages 0 PSRR (dB) -30 10 1 10 100 1k 10k 100k -40 -50 -60 -70 -80 1M 10M FREQUENCY (Hz) Figure 33. Output Noise Spectral Density vs. Frequency, ILOAD = 10 mA NOISE SPECTRAL DENSITY (nV/Hz) -20 100 100k 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz -10 1k 1 11849-028 PSRR (dB) -40 11849-031 NOISE SPECTRAL DENSITY (nV/Hz) 10k 100A 1mA 10mA 100mA 200mA 10k 1k 100 10 11849-029 Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, VOUT = 5 V, for Different Frequencies 1 10k 100k 1M 100k NOISE SPECTRAL DENSITY (nV/Hz) 16 12 8 4 0 100 LOAD CURRENT (mA) 1000 11849-030 RMS OUTPUT NOISE (V rms) 1k 10M Figure 34. Output Noise Spectral Density vs. Frequency, for Different Loads 10Hz TO 100kHz 100Hz TO 100kHz 10 100 FREQUENCY (Hz) 20 1 10 1.8V 3.3V 5.0V 10k 1k 100 10 1 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 35. Output Noise Spectral Density vs. Frequency for Different Output Voltages Figure 32. RMS Output Noise vs. Load Current Rev. A | Page 11 of 23 11849-033 HEADROOM VOLTAGE (V) 1 11849-032 -90 -100 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 ADP7118 Data Sheet T T 1 2 B W M20s A CH1 T 10.2% 1000mA 1 11849-034 CH1 200mA BW CH2 20mV CH1 1V BW CH2 2mV B W M4s T 10.2% A CH4 1.84V 11849-037 2 Figure 39. Line Transient Response, ILOAD = 200 mA, VOUT = 3.3 V, CH1 VIN, CH2 VOUT Figure 36. Load Transient Response, ILOAD = 1 mA to 200 mA, VOUT = 5 V, VIN = 7 V, CH1 Load Current, CH2 VOUT T T 1 2 1 CH2 2mV B M4.0s T 10.2% W A CH4 1.84V CH1 200mA BW CH2 20mV B W M20s A CH1 84mA T 10.2% 11849-038 CH1 2V BW 11849-035 2 Figure 40. Load Transient Response, ILOAD = 1 mA to 200 mA, VOUT = 1.8 V, VIN = 3 V, CH1 Load Current, CH2 VOUT Figure 37. Line Transient Response, ILOAD = 200 mA, VOUT = 5 V, CH1 VIN, CH2 VOUT T T 1 2 1 B W M20s A CH1 T 10.4% 148mA CH1 1V BW CH2 5mV M4.0s T 93.4% A CH4 2.08V Figure 41. Line Transient Response, ILOAD = 200 mA, VOUT = 1.8 V, CH1 VIN, CH2 VOUT Figure 38. Load Transient Response, ILOAD = 1 mA to 200 mA, VOUT = 3.3 V, VIN = 5 V, CH1 Load Current, CH2 VOUT Rev. A | Page 12 of 23 11849-039 CH1 200mA BW CH2 20mV 11849-036 2 Data Sheet ADP7118 THEORY OF OPERATION The ADP7118 is a low quiescent current, LDO linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. Drawing a low 180 A of quiescent current (typical) at full load makes the ADP7118 ideal for portable equipment. Typical shutdown current consumption is less than 3 A at room temperature. The ADP7118 is available in 16 fixed output voltage options, ranging from 1.2 V to 5.0 V. The ADP7118 architecture allows any fixed output voltage to be set to a higher voltage with an external voltage divider. For example, a fixed 5 V output can be set to a 6 V output according to the following equation: Optimized for use with small 2.2 F ceramic capacitors, the ADP7118 provides excellent transient performance. where R1 and R2 are the resistors in the output voltage divider shown in Figure 43. GND SENSE/ ADJ SHORT-CIRCUIT, THERMAL PROTECTION ADP7118 VIN = 7V REFERENCE SHUTDOWN VIN CIN 2.2F VOUT = 6V VOUT SENSE/ADJ 11849-040 EN (3) To set the output voltage of the adjustable ADP7118, replace 5 V in Equation 3 with 1.2 V. VOUT VIN VOUT = 5 V(1 + R1/R2) R1 2k COUT 2.2F R2 10k EN OFF Internally, the ADP7118 consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. GND SS CSS 1nF 11849-041 ON Figure 42. Internal Block Diagram Figure 43. Typical Adjustable Output Voltage Application Schematic It is recommended that the R2 value be less than 200 k to minimize errors in the output voltage caused by the SENSE/ADJ pin input current. For example, when R1 and R2 each equal 200 k and the default output voltage is 1.2 V, the adjusted output voltage is 2.4 V. The output voltage error introduced by the SENSE/ADJ pin input current is 1 mV or 0.04%, assuming a typical SENSE/ADJ pin input current of 10 nA at 25C. The ADP7118 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN. Rev. A | Page 13 of 23 ADP7118 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP7118 is designed for operation with small, space-saving ceramic capacitors, but functions with general-purpose capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 2.2 F capacitance with an ESR of 0.3 or less is recommended to ensure the stability of the ADP7118. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP7118 to large changes in load current. Figure 44 shows the transient responses for an output capacitance value of 2.2 F. Figure 45 depicts the capacitance vs. voltage bias characteristic of an 0805, 2.2 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~15% over the -40C to +85C temperature range and is not a function of package or voltage rating. 2.5 2.0 1.5 1.0 0.5 T 0 0 2 4 6 8 10 DC BIAS VOLTAGE (V) 1 12 11849-043 The ADP7118 is supported by the ADIsimPowerTM design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and parts count, taking into consideration the operating conditions and limitations of the IC and all real external components. For more information about, and to obtain ADIsimPower design tools, visit www.analog.com/ADIsimPower. tured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V to 100 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. CAPACITANCE (F) ADIsimPOWER DESIGN TOOL Figure 45. Capacitance vs. Voltage Characteristic Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. 2 CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) B W M20s A CH1 T 10.2% 100mA where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. 11849-042 CH1 200mA BW CH2 20mV (4) Figure 44. Output Transient Response, VOUT = 5 V, COUT = 2.2 F, CH1 Load Current, CH2 VOUT Input Bypass Capacitor Connecting a 2.2 F capacitor from VIN to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance is encountered. If greater than 2.2 F of output capacitance is required, increase the input capacitor to match it. Input and Output Capacitor Properties Any good quality ceramic capacitors can be used with the ADP7118, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufac- In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 2.09 F at 5 V, as shown in Figure 45. These values in Equation 1 yield CEFF = 2.09 F x (1 - 0.15) x (1 - 0.1) = 1.59 F (5) Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP7118, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Rev. A | Page 14 of 23 Data Sheet ADP7118 PROGRAMABLE PRECISION ENABLE The ADP7118 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 46, when a rising voltage on EN crosses the upper threshold, nominally 1.2 V, VOUT turns on. When a falling voltage on EN crosses the lower threshold, nominally 1.1 V, VOUT turns off. The hysteresis of the EN threshold is approximately 100 mV. The ADP7118 uses an internal soft start (SS pin open) to limit the inrush current when the output is enabled. The start-up time for the 3.3 V option is approximately 380 s from the time the EN active threshold is crossed to when the output reaches 90% of its final value. As shown in Figure 48, the start-up time is dependent on the output voltage setting. 6 VEN VOUT = 1.8V VOUT = 3.3V VOUT = 5.0V 3.5 5 3.0 4 VOUT (V) 2.0 3 2 1.5 1.0 1 -40C +25C +125C 1.10 1.15 1.20 1.25 0 1.30 VEN (V) The upper and lower thresholds are user programmable and can be set higher than the nominal 1.2 V threshold by using two resistors. The resistance values, REN1 and REN2, can be determined from REN2 = nominally 10 k to 100 k (6) REN1 = REN2 x (VIN - 1.2 V)/1.2 V (7) where: VIN is the desired turn-on voltage. OFF SENSE/ADJ REN1 200k REN2 100k EN 0.6 0.7 0.8 0.9 1.0 Figure 48. Typical Start-Up Behavior An external capacitor connected to the SS pin determines the soft start time. This SS pin can be left open for a typical 380 s start-up time. Do not ground this pin. When an external soft start capacitor (CSS) is used, the soft start time is determined by the following equation: SSTIME (s) = 380 s + 0.6 x CSS (8) where CSS is in farads. 2.5 VOUT (V) VOUT = 6V R1 10k 3.0 COUT 2.2F R2 20k 2.0 1.5 VEN NO SS CAP 1nF 2nF 4.7nF 6.8nF 10nF 1.0 0.5 GND 11849-045 ON VOUT 0.5 3.5 ADP7118 VIN 0.4 0.3 TIME (ms) The hysteresis voltage increases by the factor (REN1 + REN2)/ REN1. For the example shown in Figure 47, the enable threshold is 3.6 V with a hysteresis of 300 mV. CIN 2.2F 0.2 SOFT START Figure 46. Typical VOUT Response to EN Pin Operation VIN = 8V 0.1 11849-044 0 1.05 0 11849-046 0.5 0 0 Figure 47. Typical EN Pin Voltage Divider 1 2 3 4 5 6 7 8 9 TIME (ms) Figure 46 shows the typical hysteresis of the EN pin. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. Rev. A | Page 15 of 23 Figure 49. Typical Soft Start Behavior, Different CSS 10 11849-047 VOUT (V) 2.5 ADP7118 Data Sheet NOISE REDUCTION OF THE ADP7118 IN ADJUSTABLE MODE Based on the component values shown in Figure 50, the ADP7118 has the following characteristics: The ultralow output noise of the ADP7118 is achieved by keeping the LDO error amplifier in unity gain and setting the reference voltage equal to the output voltage. This architecture does not work for an adjustable output voltage LDO in the conventional sense. However, the ADP7118 architecture allows any fixed output voltage to be set to a higher voltage with an external voltage divider. For example, a fixed 5 V output can be set to a 10 V output according to Equation 3 (see Figure 50): * * * * * * VOUT = 5 V(1 + R1/R2) * The disadvantage in using the ADP7118 in this manner is that the output voltage noise is proportional to the output voltage. Therefore, it is best to choose a fixed output voltage that is close to the target voltage to minimize the increase in output noise. Note that the measured noise reduction is less than the theoretical noise reduction. Figure 51 shows the noise spectral density of an adjustable ADP7118 set to 6 V and 12 V with and without the noise reduction network. The output noise with the noise reduction network is approximately the same for both voltages, especially beyond 100 Hz. The noise of the 6 V and 12 V outputs without the noise reduction network differs by a factor of 2 up to approximately 20 kHz. Above 40 kHz, the closed loop gain of the error amplifier is limited by its open loop gain characteristic. Therefore, the noise contribution from 20 kHz to 100 kHz is less than what it would be if the error amplifier had infinite bandwidth. This is also the reason why the noise is less than what might be expected simply based on the dc gain, that is, 70 V rms vs. 110 V rms. The adjustable LDO circuit can be modified to reduce the output voltage noise to levels close to that of the fixed output ADP7118. The circuit shown in Figure 50 adds two additional components to the output voltage setting resistor divider. CNR and RNR are added in parallel with R1 to reduce the ac gain of the error amplifier. RNR is chosen to be small with respect to R2. If RNR is 1% to 10% of the value of R2, the minimum ac gain of the error amplifier is approximately 0.1 dB to 0.8 dB. The actual gain is determined by the parallel combination of RNR and R1. This gain ensures that the error amplifier always operates at slightly greater than unity gain. 100k 200k VIN VOUT R1 100k + CNR 1F SENSE/ADJ EN/ UVLO R2 100k +C VOUT = 10V OUT 2.2F RNR 10k 100k 11849-048 GND Figure 50. Noise Reduction Modification The noise of the adjustable LDO is found by using the following formula, assuming the noise of a fixed output LDO is approximately 11 V. Noise = 11 V x (RPAR + R2)/R2 where RPAR is a parallel combination of R1 and RNR. (9) 12V NOISE REDUCTION 12V NO NOISE REDUCTION 6V NOISE REDUCTION 6V NO NOISE REDUCTION 10k 1k 100 10 1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 11849-100 ON OFF CIN + 2.2F NOISE SPECTRAL DENSITY (nV/Hz) CNR is chosen by setting the reactance of CNR equal toR1 - RNR at a frequency between 1 Hz and 50 Hz. This setting places the frequency where the ac gain of the error amplifier is 3 dB down from its dc gain. VIN = 12V DC gain of 10 (20 dB) 3 dB roll-off frequency of 1.75 Hz High frequency ac gain of 1.099 (0.82 dB) Theoretical noise reduction factor of 9.1 (19.2 dB) Measured rms noise of the adjustable LDO without noise reduction is 70 V rms Measured rms noise of the adjustable LDO with noise reduction is 12 V rms Measured noise reduction of approximately 15.3 dB Figure 51. 6 V and 12 V Output Voltage with and Without Noise Reduction Network CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP7118 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP7118 is designed to current limit when the output load reaches 400 mA (typical). When the output load exceeds 400 mA, the output voltage is reduced to maintain a constant current limit. Rev. A | Page 16 of 23 Data Sheet ADP7118 Thermal overload protection is included, which limits the junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 150C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 135C, the output is turned on again, and output current is restored to its operating value. Consider the case where a hard short from VOUT to ground occurs. At first, the ADP7118 current limits, so that only 400 mA is conducted into the short. If self heating of the junction is great enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135C, the output turns on and conducts 400 mA into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between 400 mA and 0 mA that continues as long as the short remains at the output. Current and thermal limit protections protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that the junction temperature does not exceed 125C. Table 6 shows typical JA values of the 8-lead SOIC, 6-lead LFCSP, and 5-lead TSOT packages for various PCB copper sizes. Table 7 shows the typical JB values of the 8-lead SOIC, 6lead LFCSP, and 5-lead TSOT. Table 6. Typical JA Values Copper Size (mm2) 251 50 100 500 1000 6400 1 2 LFCSP 182.8 N/A2 142.6 83.9 71.7 57.4 JA (C/W) SOIC N/A2 181.4 145.4 89.3 77.5 63.2 TSOT N/A2 152 146 131 N/A2 N/A2 Device soldered to minimum size pin traces. N/A means not applicable. Table 7. Typical JB Values Model 6-Lead LFCSP 8-Lead SOIC 5-Lead TSOT JB (C/W) 24 38.8 43 To calculate the junction temperature of the ADP7118, use Equation 1. THERMAL CONSIDERATIONS TJ = TA + (PD x JA) In applications with a low input-to-output voltage differential, the ADP7118 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough to cause the junction temperature of the die to exceed the maximum junction temperature of 125C. When the junction temperature exceeds 150C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 135C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADP7118 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB. where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) (10) where: VIN and VOUT are input and output voltages, respectively. ILOAD is the load current. IGND is the ground current. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (11) As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125C. Figure 52 to Figure 60 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of PCB copper. Rev. A | Page 17 of 23 ADP7118 Data Sheet 140 145 120 115 105 95 85 75 65 55 6400mm 2 500mm 2 25mm 2 TJ MAX 45 35 25 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TOTAL POWER DISSIPATION (W) 2.2 2.4 60 40 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TOTAL POWER DISSIPATION (W) 130 130 JUNCTION TEMPERATURE (C) 140 120 110 100 90 80 70 6400mm 2 500mm 2 25mm 2 TJ MAX 60 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 TOTAL POWER DISSIPATION (W) 120 110 100 90 80 70 6400mm 2 500mm 2 50mm 2 TJ MAX 60 50 0 0.2 135 JUNCTION TEMPERATURE (C) 130 120 110 100 90 80 70 6400mm 2 500mm 2 25mm 2 TJ MAX 60 50 0.6 0.8 1.0 1.2 1.0 1.2 1.4 TOTAL POWER DISSIPATION (W) 1.6 1.8 125 115 105 95 85 6400mm 2 500mm 2 50mm 2 TJ MAX 75 11849-051 JUNCTION TEMPERATURE (C) 145 0.4 0.8 Figure 56. SOIC, TA = 50C 140 0.2 0.6 0.4 TOTAL POWER DISSIPATION (W) Figure 53. LFCSP, TA = 50C 0 4.5 Figure 55. SOIC, TA = 25C 140 11849-050 JUNCTION TEMPERATURE (C) Figure 52. LFCSP, TA = 25C 4.0 11849-155 0.2 80 Figure 54. LFCSP, TA = 85C 65 0 0.1 0.2 0.3 0.4 0.5 Figure 57. SOIC, TA = 85C Rev. A | Page 18 of 23 0.6 TOTAL POWER DISSIPATION (W) 0.7 0.8 11849-156 0 100 11849-052 JUNCTION TEMPERATURE (C) 125 11849-049 JUNCTION TEMPERATURE (C) 135 Data Sheet ADP7118 The typical value of JB is 24C/W for the 8-lead LFCSP package, 38.8C/W for the 8-lead SOIC package, and 43C/W for the 5-lead TSOT package. 145 125 115 140 105 95 65 55 500mm 2 100mm 2 50mm 2 TJ MAX 45 35 25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 TOTAL POWER DISSIPATION (W) 100 80 60 40 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 20 Figure 58. TSOT, TA = 25C 0 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TOTAL POWER DISSIPATION (W) 4.0 140 110 80 70 500mm 2 100mm 2 50mm 2 TJ MAX 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 TOTAL POWER DISSIPATION (W) 100 80 60 40 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 20 Figure 59. TSOT, TA = 50C 0 145 0 135 0.5 1.0 1.5 2.0 TOTAL POWER DISSIPATION (W) 2.5 3.0 11849-161 90 JUNCTION TEMPERATURE (C) 120 100 60 Figure 62. SOIC Junction Temperature Rise, Different Board Temperatures 125 140 115 85 500mm 2 100mm 2 50mm 2 TJ MAX 75 65 0 0.05 0.10 0.15 0.20 0.25 0.30 TOTAL POWER DISSIPATION (W) 0.35 0.40 100 80 60 40 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 20 Figure 60. TSOT, TA = 85C 0 In the case where the board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise (see Figure 61, Figure 62, and Figure 63). Calculate the maximum junction temperature by using Equation 2. 0 0.5 1.0 1.5 2.0 TOTAL POWER DISSIPATION (W) 2.5 11849-162 95 JUNCTION TEMPERATURE (C) 120 105 11849-159 JUNCTION TEMPERATURE (C) 4.5 Figure 61. LFCSP Junction Temperature Rise, Different Board Temperatures 120 11849-158 JUNCTION TEMPERATURE (C) 130 11849-160 75 JUNCTION TEMPERATURE (C) 120 85 11849-157 JUNCTION TEMPERATURE (C) 135 Figure 63. TSOT Junction Temperature Rise, Different Board Temperatures TJ = TB + (PD x JB) Rev. A | Page 19 of 23 ADP7118 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Use of 0805 or 1206 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. 11849-263 Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP7118. However, as listed in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 11849-164 Figure 64. Example LFCSP PCB Layout Figure 65. Example SOIC PCB Layout Rev. A | Page 20 of 23 ADP7118 11849-165 Data Sheet Figure 66. Example TSOT PCB Layout Table 8. Recommended LDOs for Very Low Noise Operation IOUT (mA) 300 IQ at IOUT (A) 750 IGND-SD Max (A) 75 Soft Start No PGOOD Yes Noise (Fixed) 10 Hz to 100 kHz (V rms) 15 1.22 to 19 500 900 75 No Yes 15 60 40 dB 1.8, 3.3, 5 1.22 to 19 500 900 75 Yes Yes 15 60 40 dB 2.7 to 20 1.2 to 5 1.2 to 19 200 160 10 Yes No 11 68 50 dB ADP7142 2.7 to 40 1.2 to 5 1.2 to 39 200 160 10 Yes No 11 68 50 dB ADP7182 -2.7 to -28 -1.8 to -5 -1.22 to -27 -200 -650 -8 No No 18 45 45 dB Device Number ADP7102 VIN Range (V) 3.3 to 20 VOUT Fixed (V) 1.5 to 9 ADP7104 3.3 to 20 1.5 to 9 ADP7105 3.3 to 20 ADP7118 VOUT Adjust (V) 1.22 to 19 PSRR 100 kHz (dB) 60 PSRR 1 MHz 40 dB Table 9. Related Devices Model ADP7142CP ADP7142RD ADP7142UJ ADP7112CB Input Voltage (V) 2.7 to 40 2.7 to 40 2.7 to 40 2.7 to 20 Output Current (mA) 200 200 200 200 Rev. A | Page 21 of 23 Package 6-Lead LFCSP 8-Lead SOIC 5-Lead TSOT 4-Lead WLCSP Package 3 x 3mm 8-lead LFCSP, 8-lead SOIC 3 x 3mm 8-lead LFCSP, 8-lead SOIC 3 x 3mm 8-lead LFCSP, 8-lead SOIC 2 x 2mm 6-lead LFCSP, 8-lead SOIC, 5-lead TSOT 2 x 2mm 6-lead LFCSP, 8-lead SOIC, 5-lead TSOT 2 x 2mm 6-lead LFCSP, 3 x 3mm 8-lead LFCSP, 5-lead TSOT ADP7118 Data Sheet OUTLINE DIMENSIONS 1.70 1.60 1.50 2.10 2.00 SQ 1.90 0.65 BSC 6 4 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 3 TOP VIEW 0.60 0.55 0.50 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE 0.35 0.30 0.25 0.20 MIN 1 BOTTOM VIEW 0.20 REF 02-06-2013-D PIN 1 INDEX AREA 0.15 REF Figure 67. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2.00 mm x 2.00 mm Body, Ultra Thin, Dual Lead (CP-6-3) Dimensions shown in millimeters 5.00 4.90 4.80 2.29 0.356 6.20 6.00 5.80 5 4.00 3.90 3.80 2.29 0.457 4 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW 1.65 1.25 1.75 1.35 SEATING PLANE 0.51 0.31 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 8 0 45 0.25 0.17 1.04 REF 1.27 0.40 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 68. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters Rev. A | Page 22 of 23 06-02-2011-B 8 Data Sheet ADP7118 2.90 BSC 5 4 2.80 BSC 1.60 BSC 1 2 3 0.95 BSC 1.90 BSC *1.00 MAX 0.10 MAX 0.50 0.30 0.20 0.08 SEATING PLANE 8 4 0 0.60 0.45 0.30 *COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. 100708-A *0.90 MAX 0.70 MIN Figure 69. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP7118ACPZN-R7 ADP7118ACPZN-1.8-R7 ADP7118ACPZN-2.5-R7 ADP7118ACPZN-3.3-R7 ADP7118ACPZN-5.0-R7 ADP7118ARDZ ADP7118ARDZ-R7 ADP7118ARDZ-1.8 ADP7118ARDZ-1.8-R7 ADP7118ARDZ-2.5 ADP7118ARDZ-2.5-R7 ADP7118ARDZ-3.3 ADP7118ARDZ-3.3-R7 ADP7118ARDZ-5.0 ADP7118ARDZ-5.0-R7 ADP7118AUJZ-R2 ADP7118AUJZ-R7 ADP7118AUJZ-1.8-R7 ADP7118AUJZ-2.5-R7 ADP7118AUJZ-3.3-R7 ADP7118AUJZ-5.0-R7 ADP7118UJ-EVALZ ADP7118CP-EVALZ ADP7118RD-EVALZ Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V)2, 3 Adjustable (1.2 V) 1.8 2.5 3.3 5 Adjustable (1.2 V) Adjustable (1.2 V) 1.8 1.8 2.5 2.5 3.3 3.3 5 5 Adjustable (1.2 V) Adjustable (1.2 V) 1.8 2.5 3.3 5 3.3 3.3 3.3 1 Package Description 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 6-Lead LFCSP_UD 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT TSOT Evaluation Board LFCSP Evaluation Board SOIC Evaluation Board Z = RoHS compliant part. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. 3 The evaluation boards are preconfigured with an adjustable ADP7118. 2 (c)2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11849-0-12/14(A) Rev. A | Page 23 of 23 Package Option CP-6-3 CP-6-3 CP-6-3 CP-6-3 CP-6-3 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 Branding LP9 LPA LPB LPC LPD LP9 LP9 LPA LPB LPC LPD Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADP7118ARDZ-2.5-R7 ADP7118ARDZ-3.3-R7 ADP7118ARDZ-R7 ADP7118ARDZ-1.8-R7 ADP7118ARDZ-5.0-R7 ADP7118ACPZN1.8-R7 ADP7118ACPZN2.5-R7 ADP7118ACPZN3.3-R7 ADP7118ACPZN5.0-R7 ADP7118ACPZNR7 ADP7118AUJZ-1.8-R7 ADP7118AUJZ-2.5-R7 ADP7118AUJZ-3.3-R7 ADP7118AUJZ-5.0-R7 ADP7118AUJZ-R7 ADP7118CP-EVALZ ADP7118RD-EVALZ ADP7118UJ-EVALZ ADP7118ARDZ-2.5 ADP7118ARDZ-3.3 ADP7118ARDZ-1.8 ADP7118ARDZ-5.0